Cross-Coupled Pulse Clock Generator for PVT-Stable Timing
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Solution Overview
Problem
Phase locked loop (PLL) based clock generators lack flexibility in responding to process, voltage, and temperature changes in integrated circuit (IC) chips, leading to instability in clock signal frequency.
Innovation Solution
A clock generator circuit with cross-coupled first and second pulse generators, each having ring oscillator modules, edge capture modules, and controllers to generate pulses with adjustable delay times based on inversion counts, allowing for flexible clock signal generation that adapts to IC chip changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL based clock generator is used, then the clock signal frequency is stable, but the system lacks flexibility in responding to process, voltage, and temperature changes
Solution Approach 1:
The patent implements a dynamic clocking system where the clock period is continuously adjusted based on real-time performance monitoring. The system transitions from a static PLL-based approach to a dynamic regime where clock generators can be individually enabled or disabled, and clock periods can be adjusted, allowing the system to adapt flexibly to changing process, voltage, and temperature conditions while maintaining stability through controlled optimization.
Solution Approach 2:
The system changes the clock period parameter dynamically based on monitored performance metrics. By adjusting the clock period in response to detected timing violations or performance degradation, the system maintains reliable operation across varying PVT conditions. This parameter adaptation allows the clocking system to respond to environmental changes while preserving frequency stability through controlled adjustment rather than rigid fixation.
2Productivity
If the clock period is reduced to increase operating speed, then productivity increases, but the risk of delay errors and heat-related issues increases
Solution Approach 1:
The patent implements comprehensive feedback mechanisms where performance monitors detect timing violations and trigger corrective actions. When delay errors are detected, the system responds by adjusting clock periods or disabling affected clock generators, creating a feedback loop that prevents error propagation. This feedback control allows the system to operate at high speeds while automatically correcting or preventing delay errors before they compromise reliability.
Solution Approach 2:
The system employs performance monitors that proactively detect potential timing violations before they result in functional errors. By monitoring critical paths and detecting early signs of timing degradation, the system can adjust clock parameters in advance to prevent delay errors. This proactive approach cushions against the harmful effects of high-speed operation by preparing corrective measures before actual failures occur.
Data Source
AI summary
Aspects of the disclosure provide a clock generator circuit that includes a first pulse generator and a second pulse generator cross-coupled together. The first pulse generator is configured to output first pulses. Each first pulse has a first leading edge, a first trailing edge, and a first pulse width corresponding to a first delay time that is based on a first number of inversions. The second pulse generator is configured to output second pulses. Each second pulse has a second leading edge, a second trailing edge, and a second pulse width corresponding to a second delay time that is based on a second number of inversions. The first pulse generator outputs one of the first pulses in response to the second trailing edge, and the second pulse generator outputs one of the second pulses in response to the first trailing edge.