Cross-Coupled Fin Transistor Circuit for Semiconductor Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of fin transistors in semiconductor storage devices increases the coupling capacitance between bit lines or sense lines, leading to higher frequencies of data read and write errors due to noise interference.
Innovation Solution
A semiconductor storage device configuration is implemented using a cross-coupled circuit with p-channel fin transistors, where each transistor's gate is connected to one bit line or sense line, and its drain is indirectly connected to the other via another transistor, reducing the impact of coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fin transistors are used in semiconductor storage devices, then channel controllability is improved and ON-state current increases, but coupling capacitance between gate and drain increases leading to higher data read and write errors
Solution Approach 1:
A dummy transistor is introduced as an intermediary element between the bit line and the drain of the fin transistor. This dummy transistor acts as a buffer to isolate the coupling capacitance effect from the bit line, preventing the harmful capacitive coupling from causing data read and write errors while allowing the fin transistor to maintain its high performance characteristics
Solution Approach 2:
The harmful coupling capacitance effect is extracted and isolated by separating the direct connection between the fin transistor drain and the bit line. By removing the direct capacitive coupling path and replacing it with a transistor-based connection, the harmful effect is taken out of the signal path while the useful transistor function is preserved
2Loss of energy
If fin transistors are used to improve channel controllability, then leakage power is reduced, but the coupling capacitance between bit lines increases causing noise interference
Solution Approach 1:
The dummy transistor serves as a mediator that blocks the propagation of noise generated by coupling capacitance to the bit lines. While the fin transistor structure maintains low leakage power, the intermediary transistor prevents the capacitive noise from affecting the signal integrity on the bit lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces data read and write errors by minimizing the effect of coupling capacitance between the gate and drain of fin transistors on bit line or sense line pairs.
Implementation Method 1
a fin transistor would have a greater coupling capacitance between its gate and doped regions than a planar transistor. Specifically, as shown in FIG. 7, since the fin transistor has a structure in which the gate wraps around a portion of the fin, portions A1 and A2 of the gate will produce an extra capacitance
Data Source
AI summary
A cross-coupled circuit provided between first and second bit lines that form a bit line pair includes first to fourth fin transistors of p-channel type. The first transistor has its source connected to a first power supply and its gate connected to the second bit line. The second transistor has its source connected to the first power supply and its gate connected to the first bit line. The third transistor has its source connected to the first transistor's drain and its drain connected to the first bit line. The fourth transistor has its source connected to the second transistor's drain and its drain connected to the second bit line.