Cross-Coupled Frequency Tripler for Harmonic Suppression
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Solution Overview
Problem
Current frequency tripler circuits for millimeter wave applications face challenges in achieving high suppression of driving signal frequencies and undesired harmonics, with existing solutions like class-C tripler circuits and injection-locked oscillators offering limited harmonic rejection ratio and increased power consumption.
Innovation Solution
A tripler circuit design featuring a pair of cross-coupled bipolar transistors with specific biasing and attenuation configurations, approximating an ideal polynomial trans-characteristic to generate an output current with minimal fundamental frequency component, utilizing an envelope detector to maintain desired suppression and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a class-C biased transistor is used to generate harmonic-rich current in a frequency tripler, then the desired third harmonic component is enhanced, but the fundamental frequency component and other harmonics are poorly suppressed
Solution Approach 1:
The frequency tripling function is divided into two independent stages: a class-C biased transistor stage for generating harmonic-rich current, and a separate injection-locked oscillator stage for selecting and suppressing unwanted frequencies. This segmentation allows each stage to optimize its specific function without compromising the other.
Solution Approach 2:
An injection-locked oscillator is introduced as an intermediary component between the class-C transistor and the output. This oscillator acts as a frequency-selective mediator that generates a clean third harmonic signal while inherently suppressing the fundamental frequency and other harmonics through its resonant tank circuit.
2Object-generated harmful factors
If complex filter topologies or multiple filtering stages are cascaded to improve harmonic suppression, then the suppression performance increases, but the design complexity, area, and power consumption increase
Solution Approach 1:
The injection-locked oscillator performs dual functions: it generates the desired third harmonic frequency while simultaneously providing frequency selection and harmonic suppression through its inherent resonant tank circuit. This self-service approach eliminates the need for additional complex filtering stages.
Solution Approach 2:
The injection-locked oscillator is designed to perform multiple functions within a single circuit block: frequency multiplication, frequency selection, and harmonic suppression. This multi-functionality replaces what would otherwise require multiple separate components and complex filter topologies.
3Power
If the conduction angle of the transistor is optimized to maximize third harmonic amplitude, then the third harmonic output is enhanced, but the fundamental frequency leakage remains dominant
Solution Approach 1:
The frequency tripling function is divided into two independent stages: a class-C biased transistor stage for generating harmonic-rich current, and a separate injection-locked oscillator stage for selecting and suppressing unwanted frequencies. This segmentation allows each stage to optimize its specific function without compromising the other.
Solution Approach 2:
An injection-locked oscillator is introduced as an intermediary component between the class-C transistor and the output. This oscillator acts as a frequency-selective mediator that generates a clean third harmonic signal while inherently suppressing the fundamental frequency and other harmonics through its resonant tank circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed tripler circuit achieves significant suppression of the fundamental frequency component, with measured output power at 3f0 being 40 dB higher than the sum of output powers at f0 and 5f0 across a range of input powers, demonstrating improved harmonic rejection and reduced power consumption compared to conventional designs.
Implementation Method 1
a first and a second transistor Q1, Q2 having emitter terminals coupled to each other and to a common node 21, base terminals coupled to a first and, respectively, a second input node 22, 23 and collector terminals coupled to a first and, respectively, a second output node 24, 25
Implementation Method 2
an LC resonant circuit 15 tuned at 3f0 coupled between the collector terminal C and the output terminal 14
Implementation Method 3
utilizing an envelope detector to maintain desired suppression and reduce power consumption
Data Source
Figure 1~3B
Figure 4~5
Figure 6~7
AI summary
A circuit for tripling frequency configured to receive an input voltage (Vin) having a sinusoidal shape and a base frequency. The circuit has a first and a second transistor pair (Q1-Q4) that are cross-coupled and a trans-characteristic f(Vin) approximating a polynomial nominal trans-characteristic (1) : fVin=3AVin−4A3Vin3gm wherein gm is a transconductance of transistors of the first and second transistor pairs.