Cross-Coupled Gate Contacts for Area-Efficient Transistor Layouts
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Solution Overview
Problem
The formation of gate contact structures and cross-coupled contact structures in modern integrated circuits is challenging due to the need for precise positioning to avoid electrical shorts, which results in an area penalty and complex wiring arrangements.
Innovation Solution
The development of novel methods for forming gate contact structures and cross-coupled contact structures, where a conductive source/drain contact structure with an insulating cap is positioned above the source/drain region, and gate-to-source/drain contact structures are formed to be conductively coupled with the gate structure of adjacent transistors, allowing for positioning above the active region without creating electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CB gate contact is positioned vertically above isolation material to avoid electrical shorts, then electrical short prevention is improved, but chip area utilization deteriorates due to area penalty
Solution Approach 1:
The patent transitions from a two-dimensional planar contact arrangement to a three-dimensional vertical stacking architecture. Multiple contact structures (CA contacts, CB gate contacts, and cross-coupled contacts) are positioned at different vertical levels, allowing them to occupy the same horizontal footprint without electrical interference. This vertical dimensionality change enables higher density integration while maintaining electrical isolation between contacts.
2Area of stationary object
If the CB gate contact is positioned above the active region to reduce area penalty, then chip area utilization is improved, but the risk of electrical short between CB contact and TS conductive structures increases
Solution Approach 1:
The patent positions the CB gate contact above the active region in the vertical dimension while using isolation material and precise lateral positioning to maintain horizontal separation from TS conductive structures. This allows area-efficient placement without compromising electrical isolation, as the contacts are separated both vertically and laterally.
Solution Approach 2:
The patent introduces isolation material as an intermediary barrier between the CB gate contact and TS conductive structures. This isolation layer acts as a protective mediator that prevents direct electrical contact while allowing both structures to be positioned in proximity, enabling area-efficient design without electrical short risks.
3Adaptability or versatility
If cross-coupled contact structures are formed to create electrical short between gate electrode and source/drain region, then device functionality is improved, but positioning precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning and positioning of contact structures during the device fabrication process, establishing precise locations for CA contacts, CB gate contacts, and cross-coupled contacts before subsequent processing steps. This preliminary action ensures that the required positioning precision is achieved without requiring additional alignment steps later in the process.
Solution Approach 2:
The patent employs self-aligned fabrication techniques where contact structures are automatically positioned relative to each other through conformal deposition and etching processes. The contact openings are formed using self-aligned methods that inherently maintain the required spatial relationships, reducing the burden on external alignment precision.
Data Source
AI summary
One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.