Cross-Coupled Latch Topology for Parasitic Capacitor Decoupling
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Solution Overview
Problem
Conventional latches in digital electronics face challenges in efficiently managing parasitic capacitors, which can lead to signal coupling and interference, affecting the reliability and sharing of latch components.
Innovation Solution
The design incorporates cross-coupled invertors and a specific configuration of transistors, including pMOS and nMOS transistors, with enable transistors and parasitic capacitors management, to control signal paths and prevent coupling, allowing for reliable operation and component sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional latch configurations are used, then the latch can store data, but parasitic capacitors cause signal coupling and interference
Solution Approach 1:
The patent introduces a transmission gate as an intermediary component between the first and second invertors. This transmission gate, controlled by a control signal, selectively connects or disconnects the feedback path, thereby mediating the interaction between parasitic capacitors and preventing unwanted signal coupling while maintaining necessary signal transmission for latch operation.
2Adaptability or versatility
If latch components are shared, then resource utilization improves, but signal coupling between shared components increases
Solution Approach 1:
The patent employs dynamic control of the transmission gate through a control signal that can switch between different states. This dynamic configuration allows the latch to adaptively manage the connection between shared components, enabling component sharing when needed while dynamically preventing signal coupling by disconnecting paths when interference may occur.
Data Source
AI summary
A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.