Cross-Coupled Level Shifter for Low Duty Cycle Distortion
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Solution Overview
Problem
Conventional level shifting circuits introduce significant duty cycle distortion and have limited supply voltage margin, particularly at high signal speeds, due to variations in operating voltages, process, and temperature, which affect the balance of P-channel and N-channel transistors, leading to skew in propagation delays and reduced operational reliability.
Innovation Solution
A novel level shifter circuit employing an inverting circuit, cross-coupled level shifting latch, and SR logic gate latch, where the cross-coupled latch drives output circuitry in a double-ended fashion, allowing differential output nodes to transition within distinct voltage ranges, thereby minimizing the need to balance P-channel and N-channel transistor sizes and maintaining low duty cycle distortion skew without adjusting transistor sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifting circuits are used to shift digital signals between different supply voltages, then the signal level is successfully shifted, but significant duty cycle distortion is introduced due to unequal propagation delays for low-to-high and high-to-low transitions
Solution Approach 1:
The level shifting function is divided into two independent paths: one for low-to-high transitions and another for high-to-low transitions. Each path has its own dedicated transistors and timing control mechanisms, allowing independent optimization of each transition direction to eliminate duty cycle distortion
Solution Approach 2:
The circuit dynamically adjusts the operation mode based on the input signal transition direction. Different transistor pairs are activated depending on whether the input is transitioning low-to-high or high-to-low, with each pair optimized for its specific transition type to ensure equal propagation delays
2Manufacturing precision
If transistor sizes are adjusted to balance propagation delays for low-to-high and high-to-low transitions, then duty cycle distortion is reduced at a specific operating point, but the circuit becomes sensitive to variations in voltage, process, and temperature
Solution Approach 1:
The circuit intentionally uses asymmetric transistor sizing within each transition path, where N-channel and P-channel transistors have different size ratios optimized for their specific transition direction. This asymmetric design compensates for the inherent differences in transistor characteristics and ensures balanced propagation delays across varying operating conditions
Solution Approach 2:
The circuit changes its effective parameters (transistor resistance, capacitance, drive strength) dynamically based on the operating conditions by selecting different transistor pairs for different transition directions. This allows the circuit to maintain optimal performance across a wide range of voltages, temperatures, and process variations
3Productivity
If the level shifter circuit is designed for high speed operation at 400 MHz, then signal frequency is increased, but duty cycle distortion exceeds acceptable limits (greater than 30-70% duty cycle requirement)
Solution Approach 1:
The circuit performs preliminary timing adjustment by using dedicated timing paths and pre-charged nodes that are specifically designed to equalize the propagation delays before the signal actually transitions. This preliminary synchronization ensures that both edges of the signal arrive at the output with equal delay, maintaining duty cycle accuracy at high frequencies
Solution Approach 2:
The circuit introduces intermediary timing control elements, including dedicated control signals and intermediate buffering stages, that actively manage the timing of each transition path. These intermediaries compensate for inherent delays and ensure that high-speed transitions maintain accurate duty cycles
4Reliability
If supply voltage margin is increased to improve operational reliability, then the circuit can tolerate wider voltage variations, but the transistor size balancing becomes more difficult and duty cycle distortion increases
Solution Approach 1:
The circuit segments the voltage tolerance handling into separate paths for each transition direction, with each path having its own optimized transistor sizing and timing control. This segmentation allows each path to be independently tuned for maximum voltage margin while maintaining overall duty cycle accuracy
Data Source
AI summary
A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.