Cross-Coupled Level Shifting for Common-Mode Rejection

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Solution Overview

Problem

High voltage gate driver systems face challenges in rejecting common mode currents induced by slewing in the power supply, which interferes with differential signal transmission and limits the use of narrow pulses, leading to increased power dissipation and thermal issues.

Innovation Solution

A gate driver system with a level shifting circuit and cross-coupled current mode cancellation circuit that attenuates common mode signals through cross-coupled subtraction, allowing for the generation of adjusted signals that isolate differential mode signals and enable narrower pulse transmission without affecting power dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional level shifting circuits are used without common mode rejection, then the circuit structure is simpler, but common mode currents induced by slew in the power supply interfere with differential signal transmission and prevent narrow pulse generation

Engineering Contradiction:
Improvesignal transmission accuracyVSAvoidcircuit structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces a common mode rejection circuit as an intermediary component between the differential signal input and the level shifting output. This circuit specifically targets and removes common mode currents induced by power supply slew, allowing narrow differential pulses to pass through without interference while maintaining the overall circuit functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The level shifting circuit is segmented into distinct functional blocks: a differential signal path and a common mode rejection path. The common mode rejection circuit processes the power supply slew separately and subtracts it from the main signal path, enabling independent optimization of each function without requiring complete circuit redesign.

Inventive Principle:
Principle #1Segmentation

2Speed

If narrow pulses are used for gate control, then switching speed is improved, but common mode currents interfere with signal transmission and cause thermal issues

Engineering Contradiction:
Improveswitching speedVSAvoidpower dissipation
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent converts the harmful common mode currents into a measurable signal that can be rejected. By detecting the common mode component and actively subtracting it from the differential signal path, the circuit transforms what would be interference into a controlled correction, enabling narrow pulse transmission without the usual thermal penalties.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Manufacturing precision

If filters are added to block common mode currents, then signal transmission is improved, but the circuit complexity increases and power dissipation is not minimized

Engineering Contradiction:
Improvesignal transmission accuracyVSAvoidcircuit structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent replaces passive filtering mechanisms with an active common mode rejection system. Instead of using RC filters or LC circuits that would add complexity and power consumption, the invention uses active circuitry to detect and subtract common mode currents, achieving better signal transmission with minimized power dissipation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10116301B2Cross-coupled, narrow pulse, high voltage level shifting circuit with voltage domain common mode rejection
Publication Date: 2018.10.30 INFINEON TECHNOLOGIES AMERICAS CORP
  • US10116301B2 patent drawing
  • US10116301B2 patent drawing
  • US10116301B2 patent drawing

AI summary

A system for high voltage level shifting includes a level shifting circuit having a high side circuit that receives a mixed signal having a common mode signal and a differential mode signal, and to attenuate the common mode signal in the mixed signal to generate an adjusted signal. The high side circuit generates a high output signal at a high output node in response to the adjusted signal. The system further includes a high side high voltage power transistor having a gate connected to the high output node of the high side circuit. The high side high voltage power transistor configured to provide a high portion of an output signal on a first output node in response to the high output signal.