Cross-Coupled Ring Oscillator for Low-Jitter CML Clock Generation
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Solution Overview
Problem
Existing ring oscillators in semiconductor devices generate CMOS level clock signals, which are not suitable for high-speed operations with low jitter characteristics, whereas Current Mode Logic (CML) level clock signals are preferred for their power efficiency and low jitter characteristics.
Innovation Solution
A ring oscillator with a cross-coupled buffer structure that generates CML level clock signals using a bias voltage, allowing for reduced power consumption and low jitter characteristics, and a multi-phase clock correction circuit that corrects phase differences and frequency of reference phase clock signals to produce multi-phase clock signals with predetermined phase differences and frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional ring oscillator with inverters is used, then it can generate oscillating clock signals, but the clock signals are at CMOS level which consume more power and have higher jitter characteristics
Solution Approach 1:
The patent changes the voltage level parameter of the clock signal from CMOS level to CML level by modifying the ring oscillator circuit structure. This parameter change enables the clock signal to operate at a lower voltage swing (e.g., 0.8V peak-to-peak instead of full rail-to-rail), which directly reduces power consumption and improves jitter characteristics while maintaining the oscillation function.
Solution Approach 2:
The patent segments the conventional inverter-based ring oscillator into separate functional blocks: differential buffer units with cross-coupled transistors, current sources, and load resistors. This segmentation allows each component to be optimized for CML level operation, enabling low-power and low-jitter performance while maintaining the oscillation function.
2Speed
If a ring oscillator with even number of inverters is used, then it can generate multi-phase clock signals, but it cannot generate CML level clock signals suitable for high-speed operations
Solution Approach 1:
The patent changes the voltage level and signal type parameters from CMOS to CML by using differential buffer units with cross-coupled transistors and current sources. This enables the ring oscillator to generate CML level clock signals suitable for high-speed operations while maintaining multi-phase signal generation capability through the even-numbered differential buffer structure.
3Ease of manufacture
If CMOS level clock signals are generated, then the circuit can operate with simple inverter structure, but the power consumption is high and jitter characteristics are poor
Solution Approach 1:
The patent segments the circuit into differential buffer units with cross-coupled transistors, current sources, and load resistors. While this increases structural complexity compared to simple inverters, each segment is optimized for efficient CML level operation, achieving low power consumption and low jitter. The differential structure provides inherent noise rejection and stability.
Solution Approach 2:
The patent replaces the CMOS inverter mechanism with a differential buffer mechanism using cross-coupled transistors and current sources. This substitution enables CML level signal generation, which consumes less power and has better jitter characteristics, while the differential structure provides robustness against process variations and temperature changes.
Data Source
AI summary
A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.