Cross-Coupled Voltage Conversion Circuit for Wide VDDIO Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing voltage conversion circuits in integrated circuits suffer from slow output speed and high power consumption, and are unable to meet the requirements of a wide VDDIO range, leading to instability and increased failure probability due to voltage fluctuations.
Innovation Solution
A voltage conversion circuit comprising multiple PMOS and NMOS transistors and a phase inverter, configured in a cross-coupled structure with dynamically pre-charged input follower MOS devices, which allows for efficient voltage conversion across a wide VDDIO range of 1.6V to 3.6V, ensuring high output speed and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single VDDIO is used in the voltage conversion circuit, then the circuit structure is simple, but the output speed is slow and cannot meet the requirements of wide VDDIO range
Solution Approach 1:
The voltage conversion circuit is divided into multiple parallel conversion channels, each handling a specific VDDIO voltage range. This segmentation allows each channel to be optimized for its specific range while collectively covering a wide overall range, thereby improving output speed without requiring a single overly complex circuit design.
Solution Approach 2:
The circuit dynamically selects which conversion channel to use based on the actual VDDIO voltage level. By enabling only the appropriate channel for the current voltage range, the circuit achieves fast response and high output speed while maintaining relatively simple structure through selective activation rather than all channels being active simultaneously.
2Adaptability or versatility
If VDDIO is greatly reduced or increased, then the voltage conversion range is extended, but high/low level cannot be output normally and output stability deteriorates
Solution Approach 1:
Each voltage conversion channel is designed with specific PMOS and NMOS transistor configurations optimized for its particular VDDIO range. This local optimization ensures that each channel maintains stable and reliable high/low level output within its designated voltage range, preventing the stability deterioration that would occur if a single circuit tried to handle all voltage extremes.
Solution Approach 2:
The circuit changes its operational parameters by switching between different conversion channels based on the VDDIO voltage level. Each channel has tailored transistor sizing and configuration parameters that are optimal for its specific voltage range, allowing the overall system to maintain stable output across the wide voltage range without the instability that would result from using fixed parameters for all conditions.
3Adaptability or versatility
If voltage fluctuation occurs in power supply, then the voltage conversion function is maintained, but output stability of pull-down NMOS and pull-up PMOS deteriorates and failure probability increases
Solution Approach 1:
The circuit design anticipates voltage fluctuations by incorporating redundant conversion channels that can take over if one channel becomes unstable. This beforehand preparation through redundant design cushions against failures, maintaining reliable transistor output stability even when voltage fluctuations occur during operation.
Solution Approach 2:
The phase inverter acts as an intermediary stage between the input signal and the output transistors. It buffers and conditions the signal before it reaches the pull-up PMOS and pull-down NMOS, reducing the direct impact of voltage fluctuations on these output transistors and thereby improving their stability and reducing failure probability.
4Device complexity
If current mirror structure is used for voltage conversion, then the circuit is simple, but leakage current becomes very large when input signal is at high level
Solution Approach 1:
The invention extracts and removes the problematic current mirror structure from the voltage conversion circuit. By replacing it with a direct parallel channel architecture using phase inverter and dedicated PMOS/NMOS pairs, the design eliminates the source of excessive leakage current while keeping the overall circuit structure relatively simple through modular organization.
Data Source
AI summary
The present disclosure provides a voltage conversion circuit and a chip. The voltage conversion circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a phase inverter; the source of the first PMOS transistor is connected to an I/O power supply, the drain thereof is connected with a first node, and the gate thereof is connected with a second node; the drain of the first NMOS transistor is connected with the first node, the source thereof is grounded, and the gate thereof is connected to an input signal.