Cross-CPU Data Transfer via Expansion Memory Interrupts
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Solution Overview
Problem
Conventional multi-CPU systems face limitations in data transfer speed and complexity due to direct communication methods, especially when dealing with large data segments and slow write times on devices like solid-state drives, leading to high latency and overhead in inter-CPU communication.
Innovation Solution
The implementation of an expansion memory (EM) device with a cross-CPU interrupting DMA engine facilitates high-speed data transfer between CPUs by using DMA operations and an interrupt mechanism to notify CPUs of data transfer events, allowing for efficient data sharing and simplifying messaging through an intermediate storage area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If direct communication between CPUs is used for data transfer, then data sharing between applications on separate CPUs is enabled, but transfer speed and data volume are limited by message size constraints and transfer speed limitations
Solution Approach 1:
The patent introduces a centralized server as an intermediary component that mediates data transfer between CPUs. Instead of direct CPU-to-CPU communication, data flows through the server which manages the transfer process, thereby overcoming message size constraints and speed limitations of direct communication paths.
Solution Approach 2:
The patent adds a spatial dimension to data transfer by introducing an intermediate storage layer (the server) between source and destination CPUs. This creates a multi-hop transfer path that bypasses the limitations of direct single-hop communication, enabling larger data volumes to be transferred.
2Quantity of substance
If a centralized server is used to store large amounts of data during transfer, then data transfer capacity is increased, but system complexity increases due to navigating different protocols for storage devices
Solution Approach 1:
The patent extracts the protocol complexity from the CPU system by placing it in the centralized server. The server handles all protocol-specific operations for storage devices like SSDs, isolating this complexity from the CPU applications and simplifying the overall system architecture.
Solution Approach 2:
The centralized server autonomously manages data storage and transfer protocols without requiring CPU intervention. The server's DMA engine and controller automatically handle protocol navigation, write operations, and data management, reducing the burden on CPU resources.
3Quantity of substance
If centralized server with DMA engine is used for data transfer, then data transfer capability is enhanced, but overhead and latency increase in inter-CPU communication
Solution Approach 1:
The patent implements preliminary action through the server's buffer memory that pre-stores data before transfer is needed. The DMA engine prepares data in advance in the buffer, and the interrupt mechanism pre-notifies destination CPUs, reducing wait times and latency during actual data transfer operations.
Solution Approach 2:
The patent ensures continuous data flow through the server's buffer memory that maintains data availability throughout the transfer process. The DMA engine continuously transfers data from source to buffer to destination without idle periods, and the interrupt mechanism ensures continuous notification to destination CPUs, eliminating gaps in the transfer chain.
Data Source
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AI summary
A method implemented in a memory device, wherein the memory device comprises a first memory and a second memory, the method comprising receiving a direct memory access (DMA) write request from a first central processing unit (CPU) in a first computing system, wherein the DMA write request is for a plurality of bytes of data, in response to the DMA write request receiving the plurality of bytes of data from a memory in the first computing system without processing by the first CPU, and storing the plurality of bytes of data in the first memory, and upon completion of the storing, sending an interrupt message to a second CPU in a second computing system, wherein the interrupt message is configured to interrupt processing of the second CPU and initiate transfer of the plurality of bytes of data to a memory in the second computing system.