Cross-Domain ESD Protection Circuit Using Blocking Transistor
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Solution Overview
Problem
Advanced semiconductor technology nodes face challenges in achieving effective cross-domain electrostatic discharge (ESD) protection due to the thin gate oxide of transistors, which can be damaged during ESD events, especially when the local CDM clamp cannot turn on fast enough to protect the gate oxide of the CMOS inverter in the analogue domain.
Innovation Solution
A semiconductor device with a blocking transistor connected between the first domain power rail and the signal line, and a power rail clamp that applies a control signal to the gate of the blocking transistor to prevent ESD current from flowing through the signal line during an ESD event, allowing the ESD current to be discharged through the power rail clamp to the ground rail, thereby protecting the delicate internal circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a local CDM clamp is provided to protect against ESD zapping from the analogue domain ground rail to the digital domain power rail, then ESD protection is improved, but the gate oxide of transistors may still be damaged during cross-domain ESD events
Solution Approach 1:
A blocking transistor is introduced as an intermediary component between the digital domain power rail and the signal line. This blocking transistor is controlled by a power rail clamp to prevent ESD current from reaching the signal line and damaging the gate oxide of transistors in the CMOS inverter, while still allowing normal signal operation.
Solution Approach 2:
The power rail clamp detects the ESD event and activates the blocking transistor in advance before the ESD current can damage the gate oxide. The blocking transistor is turned on preemptively to block the harmful current path, protecting the vulnerable transistors before damage occurs.
2Reliability
If interface resistors or diodes are added to provide ESD protection paths, then ESD robustness is improved, but high-frequency performance is impaired and leakage is caused
Solution Approach 1:
The blocking transistor is dynamically controlled by the power rail clamp, switching between conducting and blocking states based on ESD detection. This dynamic control allows the circuit to maintain low impedance for normal high-frequency signals while providing high impedance protection during ESD events, avoiding the performance degradation associated with static resistors or diodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances ESD robustness by preventing ESD current from reaching the signal line, thus protecting the gate dielectric of transistors from damage, without the need for interface resistors or diodes, which can impair high-frequency performance and cause leakage, and ensures effective cross-domain ESD protection in advanced technology nodes.
Implementation Method 1
the power rail clamp is operable during an ESD event to apply a control signal to the gate of the blocking transistor to block an ESD current from flowing from the first domain power rail through the signal line
Implementation Method 2
a blocking transistor connected between the first domain power rail and the signal line... to block an ESD current from flowing
Implementation Method 3
the power rail clamp is operable during an ESD event to conduct an ESD current between the first domain power rail and the first domain ground rail
Data Source
AI summary
A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.