Cross-Domain Data Transmission Parity Error Correction

Solution Overview

Problem

Current cross-domain data transmission methods, such as using synchronizers and non-synchronous FIFO memories, are prone to errors due to metastability and environmental factors like electrostatic discharging and high temperatures, which affect data integrity and pointer accuracy.

Innovation Solution

A data transmission apparatus and method that calculates parity values on both transmit and receive sides to generate a control signal for resetting write and read pointers, ensuring data integrity and accuracy across different clock domains.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a non-synchronous FIFO memory is used for cross-domain data transmission, then multi-bit data can be transmitted, but the data and pointers may change to erroneous values under environmental stress and lack restoration capability

Engineering Contradiction:

Improvemulti-bit data transmission capabilityVSAvoiddata integrity under environmental stress

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by calculating and storing parity values for data and pointers before transmission occurs. The transmit-side circuit computes parity values for input data and pointer values, then stores them in the FIFO memory along with the actual data. This pre-computed parity information is available immediately when needed for error detection, eliminating the need for post-transmission error correction and enabling rapid restoration of correct values when errors are detected.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously comparing transmit-side parity values with receive-side parity values after cross-domain transmission. The receive-side circuit recalculates parity values from received data and pointers, then compares them with the stored transmit-side parity values. When discrepancies are detected, the system generates error signals that trigger restoration operations, creating a closed-loop feedback mechanism that ensures data integrity throughout the transmission process.

Inventive Principle:

Principle #23Feedback

2Reliability

If a synchronizer is used for cross-domain data transmission, then 1-bit data can be transmitted synchronously, but multi-bit data transmission becomes error-prone due to metastability

Engineering Contradiction:

Improvesynchronous transmission accuracy for 1-bit dataVSAvoidmulti-bit data transmission capability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies segmentation by dividing multi-bit data into individual bit positions, each with its own dedicated synchronizer. Instead of attempting to synchronize all bits simultaneously through a single synchronizer (which causes metastability issues), the system creates separate synchronization paths for each bit position. This allows each bit to be synchronized independently, eliminating the metastability problems that arise when multiple bits are synchronized together while still maintaining reliable multi-bit data transmission.

Inventive Principle:

Principle #1Segmentation

3Ease of operation

If traditional FIFO memory is used, then data can be stored and retrieved across clock domains, but the system lacks the ability to detect and restore errors caused by electrostatic discharge or high temperature

Engineering Contradiction:

Improvecross-domain data storage and retrievalVSAvoidvulnerability to electrostatic discharge and high temperature

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by calculating and storing parity values for data and pointers before transmission occurs. The transmit-side circuit computes parity values for input data and pointer values, then stores them in the FIFO memory along with the actual data. This pre-computed parity information is available immediately when needed for error detection, eliminating the need for post-transmission error correction and enabling rapid restoration of correct values when errors are detected.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously comparing transmit-side parity values with receive-side parity values after cross-domain transmission. The receive-side circuit recalculates parity values from received data and pointers, then compares them with the stored transmit-side parity values. When discrepancies are detected, the system generates error signals that trigger restoration operations, creating a closed-loop feedback mechanism that ensures data integrity throughout the transmission process.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12255739B2Data transmission apparatus and method of cross-domain data transmission

Publication Date: 2025.03.18 REALTEK SEMICON CORP

AI summary

A data transmission apparatus includes a transmit-side circuit and a receive-side circuit. The transmit-side circuit belongs to a first clock domain, and is configured to store a plurality of input data. The receive-side circuit belongs to a second clock domain, and is configured to read a plurality of output data from the transmit-side circuit. The transmit-side circuit is configured to calculate a transmit-side parity value according to the plurality of input data. The receive-side circuit is configured to calculate a receive-side parity value according to the plurality of output data. The receive-side circuit is configured to compare the transmit-side parity value with the receive-side parity value to generate a control signal. The transmit-side circuit and the receive-side circuit are configured to reset, according to the control signal, a write pointer of the transmit-side circuit and a read pointer of the receive-side circuit.