Cross Dram Dimm Subchannel Pairing Signal Routing
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Solution Overview
Problem
The increasing number of memory channels per server socket complicates signal routing, leading to higher costs and reduced timing margins due to increased complexity in the number of signal layers on socket packages and system boards.
Innovation Solution
Segmenting each memory channel into two independent subchannels, with shared command-bus clocks, and employing 'skip' configurations to optimize signal routing, allowing for independent operation of subchannels and reduced swizzling of signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of memory channels per server socket is increased to improve memory bandwidth, then memory bandwidth is improved, but signal routing complexity increases and timing margins are reduced
Solution Approach 1:
The patent segments each memory channel into two independent subchannels (subchannel A and subchannel B). Each subchannel can be independently routed to different DIMMs, allowing flexible signal distribution that reduces routing complexity while maintaining high memory bandwidth capacity
Solution Approach 2:
The patent introduces a new dimension of organization by pairing subchannels from different memory channels (e.g., channel 0 subchannel A with channel 1 subchannel B) to form cross-dram DIMM pairs. This dimensional reorganization optimizes signal routing paths and reduces the number of signal layers required
2Power
If the number of memory channels per server socket is increased to improve memory bandwidth, then memory bandwidth is improved, but the number of signal layers on socket package and system board increases leading to higher costs
Solution Approach 1:
By segmenting memory channels into subchannels that can share routing resources, the patent reduces the total number of signal layers required on socket packages and system boards, directly lowering manufacturing costs while maintaining high memory bandwidth
Solution Approach 2:
The patent creates universal subchannel interfaces that can be flexibly assigned to different DIMMs and memory channels. This multi-functionality allows the same routing infrastructure to support increased memory bandwidth without proportionally increasing the number of signal layers
3Power
If the number of memory channels per server socket is increased, then memory bandwidth is improved, but routing complexity makes it more difficult to match signals reducing timing margin
Solution Approach 1:
The segmentation of memory channels into independently routable subchannels allows for optimized signal path matching. Each subchannel can be routed with dedicated attention to timing requirements, improving signal matching precision and timing margins
Solution Approach 2:
The cross-dram DIMM pairing approach reorganizes signal routing in a new dimensional framework where subchannels from different channels are paired together. This enables better control over signal path lengths and impedance matching, improving timing margins
Data Source
AI summary
Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.