Hierarchical Schematic Generation for Cross-Fabric Parasitic Extraction
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Solution Overview
Problem
Design engineers face challenges in simulating integrated circuit (IC) designs across multiple design fabrics, such as IC, package, and printed circuit board (PCB), due to incompatible schematics and the difficulty in including parasitic models from different design fabrics in simulations, requiring manual creation of parasitic-aware simulation schematics and manual stitching of components.
Innovation Solution
A computer-implemented method and system that automatically generate hierarchical schematics by receiving parent and child layout fabrics and an electromagnetic model, inserting the EM model into a parent schematic, and managing interface connections, allowing for the automatic extraction and insertion of parasitic models and connectivity information across design fabrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual creation of parasitic-aware simulation schematics is performed, then parasitic models from different design fabrics can be included in simulation, but the time and effort required for schematic creation increases significantly
Solution Approach 1:
The system performs preliminary extraction of parasitic models from multiple design fabrics (IC layout, package layout, PCB layout) before schematic generation. The parasitic models are pre-processed and stored in a standardized format, allowing them to be automatically integrated into simulation schematics without manual intervention during the schematic creation phase.
Solution Approach 2:
The system enables self-service automation where the schematic generation tool automatically extracts connectivity information from layout fabrics, generates parasitic models, and stitches them into simulation schematics without requiring manual user input. The tool services itself by automatically managing the entire workflow from layout to simulation-ready schematic.
2Adaptability or versatility
If schematics from different design fabrics are transformed to be compatible, then simulation across IC, package, and PCB fabrics can be performed, but the complexity of transformation processes increases
Solution Approach 1:
The system implements a universal schematic generation framework that can handle multiple design fabrics (IC, package, PCB) through a single integrated process. The framework uses standardized data structures and common processing logic that work across all fabric types, eliminating the need for separate transformation processes for each fabric combination.
Solution Approach 2:
The system introduces an intermediate representation layer that translates connectivity information from different layout fabric formats into a standardized internal format. This intermediary representation serves as a mediator that simplifies the transformation process by providing a common language between diverse input formats and the output simulation schematic.
3Measurement precision
If EM models are extracted from multi-fabric combined geometries, then coupling effects between fabrics can be captured, but the difficulty of stitching models into multiple schematics increases
Solution Approach 1:
The system segments the EM model stitching process by assigning each extracted EM model to its corresponding parent fabric schematic based on geometric relationships. The stitching process is divided into independent tasks for each fabric-schematic pair, with automated tracking of which devices have been included in EM models to prevent duplicate inclusion across multiple schematics.
Solution Approach 2:
The system implements feedback mechanisms that track the status of device inclusion across multiple schematics. When an EM model is stitched into a parent schematic, the system automatically updates the state information and provides feedback to prevent the same device from being incorrectly included again in child schematics, ensuring consistency across the multi-fabric simulation environment.
Data Source
AI summary
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.