Cross-FET Library Cell Layout With Vertical Stacks and Orthogonal Channels

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Solution Overview

Problem

Current semiconductor manufacturing techniques face challenges in designing standard cells due to issues like capacitive coupling, electro migration, short channel effects, and inefficient use of on-die area, which hinder the automation of signal routing and power consumption optimization.

Innovation Solution

The use of vertically stacked Cross Field Effect Transistors (FETs) with orthogonal channel orientations allows for efficient layout design, reducing on-die area consumption and improving performance by utilizing a single via layer and maximizing carrier mobility, thereby addressing the limitations of traditional Fin FETs and Complementary FETs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual full-custom designs are used, then performance and signal integrity are improved, but design cycle time increases and automation is reduced

Engineering Contradiction:

Improvesignal integrityVSAvoiddesign cycle time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The design process is segmented into standardized cell libraries that can be automatically selected and placed, while critical performance aspects are handled by specialized layout rules. This segmentation allows automation for routine tasks while maintaining manual control for optimization, resolving the contradiction between automation and performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameters of standard cells based on performance requirements, adjusting dimensions, doping profiles, and layout configurations to meet signal integrity standards while maintaining automated design flow. This allows automated design with performance optimization through parameter adjustment.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If automated place-and-route tools are used, then design productivity is improved, but manufacturing precision and performance requirements are not satisfied

Engineering Contradiction:

Improvedesign productivityVSAvoidperformance requirements

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

Performance-critical parameters are predetermined and pre-configured in the standard cell library designs before automated placement and routing occurs. This preliminary action ensures that manufacturing precision requirements are built into the design from the start, while still allowing automated tools to handle the overall design productivity.

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If conventional FET layouts are used, then manufacturing is simplified, but on-die area consumption increases and short channel effects worsen

Engineering Contradiction:

Improvelayout simplicityVSAvoidon-die area

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent transitions from planar FET layouts to vertically stacked three-dimensional FET structures. This dimensional change reduces the horizontal footprint (on-die area) while maintaining manufacturability through established vertical stacking processes, directly addressing the area consumption problem without sacrificing ease of manufacture.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Quantity of substance

If Fin FET structures are used, then transistor density is improved, but power consumption increases and carrier mobility is limited

Engineering Contradiction:

Improvetransistor densityVSAvoidpower consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent changes the structural parameters from Fin FETs to Cross FETs with orthogonal channel orientations, altering the electrical characteristics to reduce power consumption while maintaining high transistor density. The parameter change in channel orientation enables better carrier mobility and reduced short channel effects, resolving the power consumption issue.

Inventive Principle:

Principle #35Parameter changes

5Speed

If channel orientation is optimized for carrier mobility, then performance is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvecarrier mobilityVSAvoidlayout complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The Cross FET structure with orthogonal channels provides universal performance benefits for both n-type and p-type devices simultaneously. The same orthogonal orientation principle applies to all devices, creating a universal design rule that simplifies manufacturing while optimizing carrier mobility for all transistors in the circuit.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240258322A1Cross field effect transistor library cell architecture design

Publication Date: 2024.08.01 ADVANCED MICRO DEVICES INC

AI summary

A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.