Cross-Fin Isolation Layer Layout for FinFET Leakage Reduction
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Solution Overview
Problem
Conventional semiconductor devices, including FinFETs, suffer from poor isolation performance due to misalignment issues in the photolithography process, leading to degraded isolation performance and leakage current in MOS transistors.
Innovation Solution
A semiconductor device fabrication method that involves forming initial fins on a substrate, creating a gate structure material layer with a trench perpendicular to the fins, and depositing an isolation layer within the trench, where the top surface of the isolation layer is higher than the fins, followed by etching to form gate structures on both sides of the isolation layer, which improves isolation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography alignment is used, then manufacturing process is simple, but isolation performance deteriorates due to misalignment
Solution Approach 1:
The method forms the isolation layer before etching the gate structures, ensuring that the isolation layer is already in place to provide proper isolation. This preliminary action prevents misalignment issues that would occur if the isolation layer were formed after gate etching, as the isolation layer serves as a reference for subsequent alignment steps.
Solution Approach 2:
The isolation layer acts as an intermediary element between the fins and the gate structures. By forming this layer first and ensuring its proper positioning, it mediates the alignment between different components, preventing the misalignment that would otherwise occur during subsequent photolithography steps.
2Reliability
If isolation layer is formed after gate etching, then process sequence is simple, but leakage current increases due to poor isolation
Solution Approach 1:
The isolation layer is formed in advance before the gate structures are etched. This preliminary formation ensures that the isolation layer is properly positioned and can effectively prevent leakage current between adjacent transistors, addressing the reliability issue without compromising overall fabrication efficiency.
3Reliability
If isolation layer top surface is lower than fin top surfaces, then etching process is simpler, but leakage current occurs due to insufficient isolation coverage
Solution Approach 1:
The isolation layer is formed with a top surface that is higher than the fin top surfaces, creating a local quality difference that ensures proper isolation coverage. This elevated isolation layer extends beyond the fin regions to provide effective electrical isolation between adjacent transistors, preventing leakage current.
Solution Approach 2:
The isolation layer is formed with sufficient height before gate etching, ensuring that it will cover the fin regions adequately. This preliminary height control prevents leakage current issues that would occur if the isolation layer were too low.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; fins on the semiconductor substrate; an isolation layer formed on the semiconductor substrate and between adjacent fins; and gate structures on sides of the isolation layer. The isolation layer has a top surface higher than top surfaces of the fins and passes through the fins along a direction perpendicular to an extending direction of the fins and in parallel with a surface of the semiconductor substrate.