Conductive Via Across Adjacent Lines for BEOL Interconnect Simplification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of manufacturing semiconductor integrated circuits (ICs) has increased due to the scaling down process, necessitating advancements in IC manufacturing to maintain efficiency and reduce costs.
Innovation Solution
The formation of an interconnect structure with a conductive via extending across adjacent conductive lines in the back-end-of-line (BEOL) of IC fabrication, utilizing a single-damascene or dual-damascene process to create electrical connections between conductive layers, enhancing manufacturing efficiency and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-step processes are used to form vias and conductive lines separately, then manufacturing precision can be maintained, but device complexity and manufacturing time increase
Solution Approach 1:
The patent combines the via formation and conductive line formation into a single etching process. The etch mask pattern is designed to define both the via openings and the conductive line trenches simultaneously, allowing both features to be created in one step rather than requiring separate etching operations. This merging reduces manufacturing process complexity while maintaining precision through the integrated pattern transfer approach.
Solution Approach 2:
The etching process is designed to perform multiple functions: it creates via openings through the dielectric layers, forms conductive line trenches, and defines the spatial relationships between these features. The single etching step serves as a universal process that accomplishes what traditionally required multiple specialized steps, thereby reducing overall device complexity.
2Manufacturing precision
If conventional separate formation processes are used for vias and conductive lines, then manufacturing precision can be maintained, but productivity decreases
Solution Approach 1:
The patent merges via formation and conductive line formation into a single etching operation. By using an etch mask that simultaneously defines both via openings and conductive line trenches, the process eliminates the need for sequential etching steps, thereby improving manufacturing efficiency and productivity while maintaining the precision required for each feature type.
Solution Approach 2:
The etching process operates continuously to create both via openings and conductive line trenches in a single pass through the dielectric layers. This continuous action eliminates idle time between separate formation processes and maximizes the utilization of the etching equipment, thereby improving overall productivity without compromising precision.
3Productivity
If scaling down is implemented to increase functional density, then productivity and cost efficiency improve, but manufacturing complexity increases
Solution Approach 1:
The patent applies the merging principle at the scaled-down level by integrating via and conductive line formation into a single etching process. This integration is particularly valuable for scaled-down geometries where process steps must be minimized to maintain alignment precision and avoid accumulation of manufacturing variations. The unified approach reduces the number of lithography and etching cycles required, thereby managing manufacturing complexity despite the increased functional density.
Solution Approach 2:
The patent resolves scaling challenges by moving to a three-dimensional interconnect architecture with conductive layers formed at different heights and angles. This dimensional transition allows for increased functional density without proportionally increasing planar manufacturing complexity, as the conductive paths are routed through the vertical dimension rather than requiring increasingly complex planar layouts.
Data Source
AI summary
A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.