Cross-Type MIM Capacitor Structure for Lower Layer Count
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Solution Overview
Problem
Conventional MIM capacitor structures in RF transceivers require a high layer count, leading to increased process costs and yield drops due to warpage issues, while also experiencing capacitance variation challenges.
Innovation Solution
A cross-type MIM capacitor structure is implemented, using a second metallization layer for both the second plate and inductor interconnection, reducing the layer count and minimizing capacitance variation by employing a third metallization layer for the inductor, thereby reducing the number of necessary layers and improving fabrication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional POG manufacturing uses nine layers (four metal layers, three passivation layers, one insulation layer, and one under bump metallization layer), then the capacitor and inductor can be formed with sufficient functionality, but the process cost increases and yield drops due to high warpage
Solution Approach 1:
The patent combines the capacitor plate function and inductor interconnection function into a single second metallization layer. The second plate of the MIM capacitor and the inductor interconnection are formed simultaneously in the same metallization layer, eliminating the need for separate dedicated layers for each function. This merging reduces the total layer count from nine to five layers while maintaining both capacitor and inductor functionality.
Solution Approach 2:
The second metallization layer serves multiple purposes: it forms the second plate of the MIM capacitor and simultaneously provides the inductor interconnection. This multi-functional design allows a single layer to fulfill what previously required multiple separate layers, reducing overall structure complexity and minimizing warpage-induced yield loss.
2Productivity
If nine layers are used for MIM capacitor and inductor formation, then sufficient capacitance and inductance performance can be achieved, but fabrication cycle time increases and process cost increases
Solution Approach 1:
The patent merges the formation of the capacitor second plate and inductor interconnection into a single simultaneous deposition step using the second metallization layer. This eliminates sequential processing steps that would otherwise be required for separate layer formations, directly reducing fabrication cycle time while maintaining both component functionalities.
Solution Approach 2:
The inductor interconnection is formed preliminarily within the second metallization layer during the capacitor fabrication process, before subsequent processing steps. This preliminary formation of the inductor interconnection eliminates the need for additional later processing steps, thereby reducing overall fabrication cycle time.
3Reliability
If nine layers are used including separate passivation and insulation layers, then proper electrical isolation can be achieved, but warpage increases causing yield drop
Solution Approach 1:
The patent reduces the number of separate passivation and insulation layers from three to one by strategically placing the single passivation layer over critical areas. This consolidation maintains electrical isolation functionality while significantly reducing the total layer count, thereby minimizing cumulative warpage and improving yield.
Solution Approach 2:
The single passivation layer is selectively positioned to provide electrical isolation only where critically needed, rather than uniformly across all layers. This localized approach maintains necessary electrical isolation while reducing overall structure thickness and warpage, achieving the same protective function with fewer layers.
Data Source
AI summary
An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.