Cross-Network Semiconductor Design for Accurate Routability Prediction
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Solution Overview
Problem
Conventional semiconductor design methods face challenges in efficiently predicting routability due to the limitations of using either graph-based or image-based neural networks, which fail to effectively capture spatial relationships and result in unnecessary routing overload or information loss.
Innovation Solution
A semiconductor design method utilizing a fusion of graph-based and image-based neural networks to encode and process chip design information, converting features between these formats to enhance routability prediction, including tasks like congestion prediction and design rule violation detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If only graph-based neural networks are used for routability prediction, then spatial relationships can be captured, but routing overload occurs and information is lost
Solution Approach 1:
The patent combines graph-based neural networks and image-based neural networks into a hybrid architecture. The graph-based component captures spatial relationships and topological information, while the image-based component processes visual patterns and layout information. By merging these two different neural network types, the system achieves comprehensive feature extraction without overloading a single network, thereby improving routability prediction accuracy while managing complexity.
2Productivity
If only image-based neural networks are used for routability prediction, then processing speed is improved, but spatial relationships are not effectively captured
Solution Approach 1:
The hybrid neural network architecture integrates image-based processing for fast visual pattern recognition with graph-based processing for accurate spatial relationship capture. The image-based component provides rapid initial processing, while the graph-based component refines the analysis by modeling topological relationships and connectivity, achieving both speed and precision in routability prediction.
3Device complexity
If single-format neural networks are used, then device complexity is reduced, but design delays increase due to inaccurate routability prediction
Solution Approach 1:
The patent segments the routability prediction task into two specialized components: an image-based neural network for processing visual layout information and a graph-based neural network for analyzing topological relationships. Each segment is optimized for its specific function, allowing parallel processing and more accurate predictions, which reduces design delays despite the increased overall system complexity.
Data Source
AI summary
A semiconductor design method and device are provided. The semiconductor design method may include inputting a first type of design data into a first neural network model; inputting a second type of design data into a second neural network model of a different type from the first neural network model; generating a fusion feature by fusing a calculation result of the second neural network model with a feature generated by calculation up through (and obtained from) a first layer of the first neural network model; inputting the fusion feature into a second layer of the first neural network that is after the first layer of the first neural network model; and performing a task related to routability of a circuit after calculation of the first neural network model based on the fusion feature is completed.