Cross OD FinFET Patterning Using Three Lithography Masks
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Solution Overview
Problem
Conventional methods for forming multi-fin FinFETs are costly and have low throughput due to the need for large contact plugs or epitaxial processes to interconnect fin ends, which limit the scalability and efficiency of integrated circuit manufacturing.
Innovation Solution
A method using three lithography masks to define and form semiconductor fins and source/drain regions, where the second mask reduces the pitch of mask strips to half, allowing for the formation of fins with increased channel width without increasing chip area, thereby enhancing manufacturing throughput and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods using large contact plugs or epitaxial processes are used to interconnect fin ends, then multi-fin FinFET structures can be formed, but manufacturing cost increases and throughput decreases
Solution Approach 1:
The patent extracts and eliminates the need for separate interconnection processes (large contact plugs or epitaxial growth) by integrating the source/drain region formation directly into the fin patterning process. The third lithography mask with its specific pattern allows the etch to simultaneously define fin structures and create open regions for source/drain contacts, removing the need for subsequent interconnection steps.
Solution Approach 2:
The patent merges the fin formation and source/drain region formation into a single etching step. The third mask layer pattern is designed so that the etch process simultaneously creates the fin structures and exposes the source/drain regions, combining what were previously separate manufacturing operations into one unified process step.
2Power
If multiple fins are formed to maximize channel width, then drive current increases, but chip area increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical structure. By forming fins that extend vertically from the substrate and connecting them through source/drain regions, the channel width is effectively increased in the vertical dimension rather than requiring proportional increases in horizontal chip area. This dimensional transition allows higher drive current with compact footprint.
Solution Approach 2:
The patent implements a nested structure where multiple fin channels are contained within a compact footprint, with source/drain regions nesting beneath and connecting the fin structures. The third mask pattern creates a configuration where fin structures and source/drain regions are interlocked in a space-efficient arrangement, maximizing channel width within minimal chip area.
3Productivity
If three lithography masks are used to form fins and source/drain regions simultaneously, then manufacturing cost decreases and throughput increases, but process complexity increases
Solution Approach 1:
The third lithography mask serves multiple functions simultaneously: it defines the boundaries of fin structures, creates openings for source/drain regions, and establishes the pattern for subsequent etching. This multi-functional mask design consolidates what would otherwise require separate patterning steps into a single operation, increasing throughput despite the apparent process complexity.
Data Source
AI summary
A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.