Cross-Over Die Interconnects for High-Density 3D Die Stacking
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Solution Overview
Problem
As semiconductor technologies advance, scaling interconnectivity between individual dies in a System-on-a-Chip (SoC) becomes challenging due to increasing I/O connections, requiring high-density, short-channel, wide interconnects that conventional methods such as post-fabrication redistribution layers and flip chip bonding cannot deliver effectively.
Innovation Solution
The use of cross-over die and through-die vias to create interconnects between dies, where an interconnect die is hybrid bonded to both dies using through-die vias, providing communication pathways and acting as a bridge to achieve high-density, short-channel connections, and additional dies are stacked face-down on these interconnects to enhance connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional post-fabrication redistribution layers and flip chip bonding are used to connect dies, then manufacturing processes are relatively simple, but the interconnect density and channel length are insufficient for advanced scaling requirements
Solution Approach 1:
The patent transitions from planar 2D interconnect architecture to 3D vertical stacking architecture. Multiple dies are stacked vertically with interconnect dies positioned between functional dies, creating three-dimensional interconnect pathways that achieve higher density and shorter channel lengths while maintaining manufacturing feasibility through established bonding processes
Solution Approach 2:
Interconnect dies are introduced as intermediary components between functional dies. These interconnect dies contain through-die vias that serve as mediators to establish electrical connections between upper and lower functional dies, enabling high-density interconnectivity without requiring direct complex bonding between all functional die pairs
2Adaptability or versatility
If the number of I/O pins and die size increase to maintain connectivity, then more functions can be integrated, but scaling becomes increasingly difficult and costly
Solution Approach 1:
The patent utilizes the vertical dimension to multiply I/O connection capacity. By stacking multiple functional dies with interconnect dies in between, the system achieves high I/O capacity without increasing the lateral footprint of individual dies. Through-die vias provide multiple connection pathways vertically, enabling scalable I/O expansion
Solution Approach 2:
The system is segmented into functional dies and interconnect dies with distinct roles. Functional dies contain computation and memory functions while interconnect dies provide connection infrastructure. This segmentation allows independent optimization of each die type and enables modular scaling where additional functional dies can be added without redesigning the entire interconnect architecture
Data Source
AI summary
A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.