Cross-Over Die Interconnects for High-Density Chiplet Links
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Solution Overview
Problem
As semiconductor technologies advance, scaling interconnectivity between individual dies in a System-on-a-Chip (SoC) becomes challenging due to increasing I/O connections and the limitations of conventional connection technologies, such as post-fabrication redistribution layers and flip chip bonding, which struggle to achieve high density and short channel connections.
Innovation Solution
The use of cross-over die and through-die vias to create interconnects between dies, where an interconnect die is bonded to through-die vias in other dies, providing high-density communication pathways and acting as a bridge between them, enabling efficient signal, power, and ground delivery, and potentially including active functional circuit blocks for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional connection technologies (post-fabrication redistribution layers and flip chip bonding) are used to connect individual dies, then the design flexibility and yield are improved, but the connection density and channel length become insufficient
Solution Approach 1:
The patent transitions from planar 2D interconnect arrangements to 3D vertical interconnect structures by stacking dies and using through-die vias. This dimensional change enables high-density connections by utilizing the vertical space dimension, allowing multiple connection layers and pathways that cannot be achieved in conventional 2D layouts.
Solution Approach 2:
The patent implements nested interconnect structures where through-die vias pass through entire die substrates, and interconnect layers are embedded within die structures. The cross-over die technique allows one die to be positioned over another with interconnects routing through and between them, creating a nested arrangement that maximizes connection density within limited space.
2Productivity
If the number of I/O pins increases to maintain connectivity as dies shrink, then the functional capability is improved, but the scalability and manufacturing difficulty deteriorate
Solution Approach 1:
The patent divides the monolithic SoC into multiple separate dies (functional segments) that are individually fabricated and then interconnected through 3D stacking. This segmentation allows each die to be optimized independently, improves manufacturing yield by isolating defects to individual dies, and enables parallel fabrication processes that enhance overall productivity.
Solution Approach 2:
The patent introduces intermediary structures including bump electrodes, solder layers, and encapsulant materials that facilitate precise alignment and connection between stacked dies. These intermediary elements act as mediators that compensate for manufacturing tolerances and enable high-precision connections without requiring extreme manufacturing precision at each interface.
3Ease of manufacture
If individual dies are separated to improve yield and reduce design complexity, then the manufacturing flexibility is improved, but the interconnect performance and efficiency worsen
Solution Approach 1:
The patent merges multiple separate dies into a unified 3D integrated structure through bonding interfaces and interconnect networks. While the dies remain physically separate for manufacturing purposes, they are functionally merged through the interconnect architecture to achieve monolithic-like performance and efficiency, combining the benefits of both separate fabrication and integrated performance.
Data Source
AI summary
A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.