Cross-Page Prefetching via TLB Prediction
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Solution Overview
Problem
Current computer systems face inefficiencies in prefetching data across virtual memory pages, leading to reduced performance due to the need to rebuild confidence levels and prefetch distances from initial values, resulting in temporary stalls and reduced efficiency when accessing data from new memory pages.
Innovation Solution
The solution allows prefetching to continue across physical memory pages by inheriting confidence levels and prefetch distances established on the previous page, either by suspending prefetching temporarily until a confirming access is made or by predicting the next virtual page number using a translation lookaside buffer, ensuring continuous prefetching with high confidence and distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prefetching is performed across physical memory pages, then prefetching efficiency and system performance are improved, but the confidence level and prefetch distance must be rebuilt from initial values at page boundaries, causing temporary stalls and reduced efficiency
Solution Approach 1:
The patent applies preliminary action by predicting the next virtual page number using a translation lookaside buffer (TLB) before actually crossing the page boundary. This allows the prefetcher to prepare prefetch operations in advance, maintaining confidence levels and prefetch distances across page boundaries without temporary stalls, thus resolving the contradiction between prefetching efficiency and latency at page boundaries
2Reliability
If prefetching is suspended temporarily to confirm the next physical memory page, then prefetching accuracy is maintained, but system performance is reduced due to interruptions in the prefetching process
Solution Approach 1:
The patent uses the translation lookaside buffer (TLB) as an intermediary to obtain physical address translations without suspending the prefetching process. The TLB provides fast translation of virtual to physical addresses, allowing the prefetcher to maintain both accuracy and continuous operation, thus resolving the contradiction between prefetching accuracy and system performance
3Loss of time
If aggressive prefetching is performed with high confidence levels and prefetch distances, then latency is reduced and performance is improved, but the risk of evicting needed cache lines increases when the cache is full
Solution Approach 1:
The patent applies dynamics by making the confidence level and prefetch distance adjustable and adaptive rather than fixed. The prefetcher can dynamically adjust these parameters based on the current cache state and access patterns, allowing aggressive prefetching when appropriate while reducing the risk of evicting needed cache lines when the cache is full, thus resolving the contradiction between latency reduction and cache line retention
Data Source
AI summary
Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that map to more than one physical memory page, then prefetching can continue from a first physical memory page to a second physical memory page. The prefetching advantageously continues to the second physical memory page based on the confidence level and prefetch distance established while the first physical memory page was the target of the access requests.