Cross-Pattern Memory Cell Wiring for Voltage Balance
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices face issues with parasitic capacitance and wiring resistance, leading to uneven voltage application across memory cells, which degrades rewriting time and data retention characteristics due to the difference in resistance loads between bit lines and source lines.
Innovation Solution
The proposed nonvolatile semiconductor memory device employs a configuration where the loads of data lines are made uniform by connecting them in a cross-pattern, ensuring the same voltage is applied to both terminals of the memory cell, regardless of the resistance state, thereby balancing voltage and reducing capacity loads for faster charging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Force
If bit lines are connected in common to variable resistance elements and disposed in a layer above, then parasitic capacitance load becomes large, but wiring resistance remains low; if source lines are connected in common to cell transistors and disposed in a layer below, then parasitic capacitance load becomes small, but wiring resistance becomes high
Solution Approach 1:
The patent applies asymmetry by intentionally creating different connection configurations for bit lines and source lines. Bit lines are connected to variable resistance elements through a direct path with low resistance, while source lines are connected to cell transistors through a path designed to minimize parasitic capacitance. This asymmetric design allows each line type to optimize for its primary electrical characteristic.
Solution Approach 2:
The patent resolves the contradiction by utilizing different spatial dimensions and layer configurations. Bit lines are disposed in upper layers with direct connections to variable resistance elements, while source lines are disposed in lower layers with optimized routing to cell transistors. This three-dimensional wiring architecture allows simultaneous optimization of both resistance and capacitance characteristics.
2Productivity
If different write voltages are applied to bit lines and source lines to set variable resistance elements, then data can be written, but uneven voltage application degrades rewriting time and data retention characteristics
Solution Approach 1:
The patent applies equipotentiality by designing the wiring architecture so that both bit lines and source lines experience equivalent electrical conditions during write operations. Through careful balancing of line lengths, routing paths, and connection points, the patent ensures that voltage drops and parasitic effects are matched between the two line types, creating equipotential conditions at critical nodes.
Solution Approach 2:
The patent utilizes parameter changes by adjusting wiring dimensions, materials, and routing configurations to balance the electrical characteristics of bit lines and source lines. By modifying parameters such as line width, length, and interconnect structure, the patent achieves matched voltage application characteristics despite the fundamentally different functions of the two line types.
3Speed
If bit lines have large capacity load, then charging cannot be performed at high speed, but reducing capacity load may increase wiring complexity
Solution Approach 1:
The patent applies segmentation by dividing the bit line into multiple segments with intermediate connection points and buffering structures. This segmentation reduces the effective capacitance that any single driver must charge, thereby improving charging speed. The segmented architecture also allows for distributed driving points, reducing the overall wiring complexity burden on any single line.
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a memory cell (MC0) including a cell transistor (TC0) and a variable resistance element (RR0); a memory cell (MC1) including a cell transistor (TC1) and a variable resistance element (RR1); a word line (WL0) connected to the cell transistor (TC0); a word line (WL1) connected to the cell transistor (TC1); a data line (SL0) connecting the cell transistor (TC0) and the variable resistance element (RR1) to each other; and a data line (BL0) connecting the variable resistance element (RR0) and the cell transistor (TC1) to each other.