Cross-Shaped Active Pillars for DRAM Gate Control
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Solution Overview
Problem
As semiconductor devices scale down, the size of transistors decreases, leading to weakened gate control capability and increased short-channel effects, which reduces the performance of semiconductor structures like DRAM.
Innovation Solution
The method involves forming active pillars with a cross-shaped projection on a substrate, increasing their surface area by forming a first oxide layer, word lines, and a contact layer, which enhances the specific surface area of the gate structure, thereby improving gate control and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension of DRAM is continuously scaled down, then the integration is optimized, but the gate control capability of transistors is weakened and short-channel effect becomes more obvious
Solution Approach 1:
The patent introduces a third-dimensional structure by forming suspended active pillars that extend vertically from the substrate. This 3D configuration increases the effective surface area of the active region without increasing the planar footprint, thereby maintaining gate control capability while enabling higher integration density. The suspended structure creates additional gate-to-channel interface area that improves electrostatic control over the channel region.
Solution Approach 2:
The patent implements a nested structure where the active pillar is suspended within a cavity formed in the substrate. The active pillar is positioned within the cavity space, and the gate structure wraps around or contacts the active pillar, creating a nested configuration. This nesting approach maximizes the use of vertical space and improves gate control by surrounding the channel region.
2Productivity
If the size of transistors is reduced, then the integration is improved, but the performance of semiconductor structure is reduced
Solution Approach 1:
By transitioning from planar 2D transistor structures to 3D suspended pillar structures, the patent achieves better performance without sacrificing integration. The vertical suspension and increased surface area provide enhanced gate control and carrier transport pathways, improving device performance while maintaining compact planar dimensions for high integration.
Solution Approach 2:
The patent employs composite material structures including the active pillar material, gate electrode materials, dielectric layers, and contact materials. This multi-material composite approach enables optimization of each component's properties to achieve superior overall device performance, with the suspended configuration allowing better material utilization and interface control.
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming active pillars arranged in an array on the substrate, a projection shape of a longitudinal section of each of the active pillars includes a cross shape; forming a first oxide layer on the substrate, where a filling region is formed between adjacent active pillars in the same row; sequentially forming a word line and a dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the active pillars; and forming a capacitor structure on the contact layer.