Cross-Plane Address Remapping for Nonvolatile Memory Bad Blocks

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Solution Overview

Problem

Flash memory devices suffer from defective or bad blocks that hinder normal operation and reduce available capacity, necessitating effective methods for processing and replacing such blocks.

Innovation Solution

A nonvolatile memory device with a first and second plane, each containing memory blocks, an address replacing circuit, and an address decoder that remaps addresses to avoid bad blocks, utilizing an address replacing circuit to convert input addresses to functional addresses for normal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bad blocks are replaced with memory blocks from the same plane, then the replacement process is simple and fast, but the available capacity is reduced because spare blocks within the same plane are limited

Engineering Contradiction:
Improvereplacement speedVSAvoidavailable capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent extends the replacement scope from a single plane to multiple planes. When a bad block occurs in the first plane, the system can replace it with a memory block from the second plane, effectively adding a dimensional perspective to the replacement process. This cross-plane replacement mechanism increases the pool of available replacement blocks without complicating the fundamental replacement logic, thus maintaining high replacement speed while preserving available capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If cross-plane replacement is implemented, then the available capacity is maintained, but the address management complexity increases

Engineering Contradiction:
Improveavailable capacityVSAvoidaddress management
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mapping mechanism between logical addresses and physical addresses across planes. The address translation layer acts as a mediator that handles cross-plane replacements transparently, mapping logical block addresses to appropriate physical blocks in either the first or second plane. This intermediary layer abstracts the complexity of cross-plane management, allowing the system to maintain full capacity while managing address translations without exposing the complexity to external controllers.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If dedicated main blocks and replica blocks are used for operational information, then the reliability of initialization is improved, but the memory structure becomes more complex

Engineering Contradiction:
Improveinitialization reliabilityVSAvoidmemory structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating specialized regions within the memory structure dedicated to specific functions. Dedicated main blocks store critical operational information while replica blocks provide redundancy. This localized specialization allows different parts of the memory structure to serve different purposes - some blocks for data storage, others for operational information, and replicas for reliability - thereby improving initialization reliability through functional differentiation without requiring complete structural redesign.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250272015A1Nonvolatile memory device and operation method thereof
Publication Date: 2025.08.28 SAMSUNG ELECTRONICS CO LTD
  • US20250272015A1 patent drawing
  • US20250272015A1 patent drawing
  • US20250272015A1 patent drawing

AI summary

Disclosed is a nonvolatile memory device which includes a first plane that includes a plurality of memory blocks, a second plane that includes a plurality of memory blocks, an address replacing circuit that receives a first input address from an external controller, the first input address corresponding to a first memory block of the plurality of memory blocks of the first plane from an external controller and outputs a replaced address based on the first input address and bad block information, and an address decoder that controls word lines connected with a second memory block based on the replaced address, the word lines corresponding to the replaced address from among the plurality of memory blocks of the second plane. The first memory block of the first plane is a bad block.