Cross Point Cell Array Patterning via Spacer Technology
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Solution Overview
Problem
Current methods for manufacturing semiconductor devices with cross point cell arrays face challenges in achieving high integration density and reliability, particularly in forming fine conductive patterns and preventing oxidation of resistive elements during processing.
Innovation Solution
The method involves a spacer patterning technology (SPT) that forms intermediate pattern structures with parallel lines and connectors, followed by gap-fill insulation and selective etching to create conductive lines and pillars, ensuring that sidewalls of resistive elements are covered to prevent oxidation during separation of conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning methods are used to form conductive patterns, then manufacturing process is simpler, but manufacturing precision deteriorates due to inability to form fine patterns
Solution Approach 1:
The patterning process is divided into multiple stages: first forming a preliminary pattern structure, then using it as a mask to form the final fine pattern. This segmentation allows each stage to be optimized independently, achieving high precision without excessive overall complexity
Solution Approach 2:
A preliminary pattern structure is formed before the final patterning step. This preliminary structure serves as a foundation and mask for subsequent fine pattern formation, enabling precise pattern transfer while simplifying the overall process
2Productivity
If conductive lines are separated to form cross point array, then integration density is improved, but reliability deteriorates due to oxidation of resistive elements
Solution Approach 1:
An insulation layer is introduced as an intermediary between the conductive lines and the resistive elements. This insulation layer acts as a protective barrier that prevents oxidation of the resistive elements while allowing the conductive lines to be separated for forming the cross point array structure
Solution Approach 2:
The insulation layer is formed in advance before the separation process, providing preliminary protection against oxidation. This preemptive measure prevents the harmful oxidation effect from occurring during the subsequent line separation and pattern formation steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density of semiconductor devices with cross point cell arrays by forming fine patterns and improves reliability by preventing oxidation of resistive elements, thus ensuring the integrity of the RRAM cell array.
Implementation Method 1
The first stack structure is etched using the first mask pattern as an etch mask to form a first intermediate pattern structure
Implementation Method 2
A first gap-fill insulation layer is formed to fill a space between the parallel line patterns of the first intermediate pattern structure
Data Source
AI summary
A method of fabricating a semiconductor device is provided. The method includes an intermediate pattern structure on a substrate. The intermediate pattern structure includes a pair of first conductive lines extending in a first direction, a pair of first conductive connectors connecting end portions the pair of first conductive lines to each other, a pair of second conductive lines intersecting the pair of first conductive lines, and a pair of second conductive connectors connecting end portions of the pair of second conductive lines to each other. The first and second conductive connectors are selectively removed using a cut mask pattern to separate the pair of first conductive lines from each other and to separate the pair of second conductive lines from each other.