3D Cross-Point Memory Array Voltage Management
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Solution Overview
Problem
High-density memory arrays face challenges with increased capacitance and resistance in control lines, leading to higher power consumption and slower operation times in cross-point memory architectures.
Innovation Solution
The implementation of a cross-point memory array with a cell structure comprising an ovonic threshold switch and phase change material, where threshold voltages are used to manage voltage dividing effects, and control circuitry applies specific voltages to access lines to minimize power consumption during write and read operations by keeping bias voltages unchanged for unselected lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory array density is increased, then storage capacity is improved, but capacitance and resistance of control lines increase leading to higher power consumption
Solution Approach 1:
The memory array is divided into multiple blocks, each with its own set of control lines. This segmentation allows only the control lines for the currently accessed block to be activated, reducing the total capacitance that needs to be charged/discharged during operations. The patent implements this by organizing memory cells into blocks and selectively enabling control lines for specific blocks during read/write operations.
Solution Approach 2:
The control circuitry dynamically adjusts the voltage levels on control lines based on whether they are selected or unselected. During transitions between read and write operations, the circuitry maintains bias voltages on unselected control lines at intermediate levels rather than fully charging or discharging them, reducing the energy required for voltage transitions. This dynamic voltage management directly addresses the power consumption issue.
2Quantity of substance
If memory array density is increased, then storage capacity is improved, but operation speed decreases due to higher capacitance and resistance
Solution Approach 1:
By segmenting the memory array into blocks with separate control lines, the patent reduces the RC time constant for each control line. Smaller control line capacitance and resistance values result in faster charging and discharging times, enabling quicker read and write operations despite the overall increased array density.
Solution Approach 2:
The control circuitry pre-charges or pre-discharges control lines to intermediate bias voltages before actual read/write operations. This preliminary action reduces the voltage swing required during actual operations, thereby reducing the time needed for control line transitions and improving overall operation speed.
3Adaptability or versatility
If voltage changes are applied to control lines during operation transitions, then operational flexibility is improved, but power consumption increases
Solution Approach 1:
The control circuitry maintains unselected control lines at intermediate bias voltages during transitions between operations, creating an equipotential state that minimizes voltage swings. This approach allows the system to maintain operational flexibility while reducing the energy required for voltage transitions, as fewer control lines need to be fully charged or discharged.
Solution Approach 2:
The patent changes the voltage parameter of control lines dynamically based on their selection state and operation type. By using intermediate bias voltages for unselected lines and only applying full voltage swings to selected lines during actual operations, the system achieves both operational flexibility and reduced power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster operation with lower power consumption by reducing the need for voltage changes during transitions between write and read operations, thereby enhancing the efficiency of the memory array.
Implementation Method 1
The cell structure comprises a switch element such as an ovonic threshold switch and a memory element of phase change material. The memory cells in the plurality have a first threshold voltage Vth(S) for selection of a cell when the selected memory cell is in a set state (lower resistance) and a second threshold voltage Vth(R) for selection of a cell when the selected memory cell is in a reset state (higher resistance).
Implementation Method 2
a memory element of phase change material
Implementation Method 3
Vth(S) and Vth(R) correspond to the thresholds for lowest and highest resistance ranges, respectively, due for example to differences in a voltage dividing effect in the cell in the set and reset states.
Data Source
AI summary
An integrated circuit includes a memory array including a plurality of memory cells disposed at respective cross points of a plurality of first access lines and a plurality of second access lines. A selected memory cell has a first threshold voltage Vth(S) of set state and a second threshold voltage Vth(R) of reset state. Control circuitry is configured to apply a write voltage Vw to the selected first access line during a write operation, to apply a read voltage Vr to the selected first access line during a read operation, and to apply a same inhibit voltage Vu to unselected first and second access lines during the write and read operations, where ½Vw>Vu>Vw−Vth(S).