Cross-Point Memory Array with Carbon Dielectric
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Solution Overview
Problem
Existing nonvolatile memory devices with resistance variable elements face design flexibility and integration limitations due to the use of field effect transistors (FETs) as access controllers, which are three-terminal devices.
Innovation Solution
The implementation of a memory array with memory cells defined at intersections of signal lines, where each memory cell includes a pillar structure with a resistance variable layer, a switching layer, an electrode layer, and a carbon containing dielectric layer with an ultra-low dielectric constant, effectively reducing parasitic capacitance and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FETs are used as access controllers for resistance variable elements, then high on/off ratio and leakage current prevention are achieved, but design flexibility and integration level are significantly limited
Solution Approach 1:
The patent extracts and removes the FET access controller from the memory cell structure, replacing it with a direct cross-point intersection of bit lines and word lines. This eliminates the three-terminal FET device while maintaining memory functionality through the inherent resistance switching characteristics of the memory elements at the intersection points, thereby significantly improving design flexibility and integration level.
Solution Approach 2:
The patent merges the access control function directly into the cross-point intersection structure itself, rather than using separate FET components. The intersection of bit lines and word lines at each memory element location serves as the access mechanism, combining the routing and selection functions into the fundamental array structure, which enhances integration density.
2Reliability
If FETs are used as access controllers, then leakage current is prevented, but integration level and design flexibility are limited
Solution Approach 1:
The patent extracts and removes the FET access controller from the memory cell structure, replacing it with a direct cross-point intersection of bit lines and word lines. This eliminates the three-terminal FET device while maintaining memory functionality through the inherent resistance switching characteristics of the memory elements at the intersection points, thereby significantly improving design flexibility and integration level.
Solution Approach 2:
The cross-point intersection structure serves its own access control function without requiring external FET components. The resistance switching elements at the intersections inherently provide the necessary on/off control when addressed by the intersecting bit and word lines, making the structure self-sufficient and eliminating the need for additional access control devices.
3Ease of manufacture
If conventional memory cell structures are used, then manufacturing is straightforward, but parasitic capacitance increases RC delay
Solution Approach 1:
The patent employs a carbon-containing dielectric layer with ultra-low dielectric constant (k < 2.0), which exhibits porous or low-density characteristics. This material reduces parasitic capacitance between adjacent memory elements and signal lines, thereby decreasing RC delay and improving signal speed while maintaining manufacturability through standard deposition processes.
Solution Approach 2:
The patent changes the dielectric constant parameter of the insulating material from conventional values (k > 2.0) to ultra-low values (k < 2.0) by using carbon-containing dielectric materials. This parameter change directly reduces parasitic capacitance and RC delay, improving memory cell performance without compromising manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances design flexibility and integration level by reducing RC delay and protecting the memory cells from manufacturing damages, while maintaining high storage density without increasing footprint area.
Implementation Method 1
a carbon containing dielectric layer, laterally surrounding a stacking structure comprising the resistance variable layer, the switching layer and the electrode layer
Data Source
AI summary
A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.