Cross-Point Memory Bias Control for Write Current Optimization
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Solution Overview
Problem
Conventional semiconductor storage devices with cross-point memory arrays face challenges in supplying a proper level of write current to target memory cells due to limitations in current driving capability of data line and bit line selecting transistors, especially when the number of bit lines increases, leading to inadequate writing characteristics and increased chip size and production costs.
Innovation Solution
The semiconductor storage device employs a bias mode where data lines and bit lines are separately driven, with specific bias voltages applied to unselected memory cells to minimize bias components and ensure adequate write current supply to selected memory cells without enlarging transistor size, by adjusting row and column selecting potentials to optimize current driving capability based on the relative current driving capabilities of data line and bit line selecting transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bit lines is increased to expand memory capacity, then the storage capacity is improved, but the current driving capability of selecting transistors becomes insufficient and chip size increases
Solution Approach 1:
The patent segments the bit line selecting transistors into multiple groups, with each group responsible for a specific range of bit lines. This segmentation allows each transistor to drive fewer bit lines, maintaining adequate current driving capability while supporting an increased total number of bit lines for expanded memory capacity.
Solution Approach 2:
The patent introduces a group selection dimension in addition to the row and column selection dimensions. By adding this fourth dimension for organizing selecting transistors into groups, the system can manage a larger number of bit lines without requiring each individual transistor to drive excessive current, thus maintaining writing characteristics while expanding capacity.
2Reliability
If the size of selecting transistors is increased to improve current driving capability, then the write current supply is improved, but the chip area and production costs increase
Solution Approach 1:
Instead of using a few large selecting transistors, the patent divides the selection function across multiple smaller transistors organized in groups. Each transistor maintains a compact size suitable for integration, while the collective group provides sufficient current driving capability through parallel operation.
Solution Approach 2:
The patent combines multiple selecting transistors in parallel within each group to achieve the required current driving capability. This merging of multiple small transistors provides equivalent or superior current capability compared to a single large transistor, while occupying less total chip area due to better layout efficiency and reduced individual transistor dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively supplies the required write current to target memory cells while minimizing transistor size and chip area, thereby enhancing writing characteristics and reducing production costs by optimizing current driving capability and power consumption.
Implementation Method 1
each memory cell consisting mainly of a variable resistor element of which the electric resistance is varied to save a data
Implementation Method 2
supplying a selected data line of the data lines connected to the memory cell to be written and unselected data lines of the data lines other than the selected data line with a row selecting potential and a row unselecting potential respectively
Data Source
AI summary
In a semiconductor storage device with cross point type arrays of memory cells including variable resistor elements, a selected data line and unselected data lines are supplied with a row selecting potential and a row unselecting potential through a data line selecting transistor respectively, a selected bit line and unselected bit lines are supplied with a column selecting potential and a column unselecting potential through a bit line selecting transistor respectively. Data lines and bit lines are separately driven so that when the data line selecting transistor is higher in the current driving capability than the bit line selecting transistor, a second bias voltage between the row unselecting potential and column selecting potential is lower than a first bias voltage between the row selecting potential and column unselecting potential, in the opposite case, the first bias voltage is lower than the second voltage.