Cross-Point Memory Biasing for Standby Power and Read Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile storage systems face challenges in reducing power consumption during standby mode and minimizing first read latency when transitioning from standby to read mode, particularly in cross-point memory arrays without isolation elements, which leads to increased leakage currents and power consumption.
Innovation Solution
A three-dimensional cross-point memory array with vertical bit lines is biased during standby mode by setting both word lines and bit lines to an unselected voltage, and during the transition to read mode, a selected word line is set to a read voltage while unselected word lines and bit lines remain at the unselected voltage, reducing leakage currents and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If cross-point memory arrays without isolation elements are used, then device complexity is reduced and manufacturing is simplified, but leakage currents increase and power consumption rises during standby mode
Solution Approach 1:
The patent applies preliminary action by pre-biasing word lines and bit lines to an unselected voltage level before read operations. This preliminary biasing establishes a stable baseline state that minimizes leakage currents during standby mode while preparing the memory array for rapid transition to read mode, thereby reducing both power consumption and first read latency without requiring isolation elements
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting voltage levels on word lines and bit lines between standby and read modes. During standby, all lines are biased to an unselected voltage to minimize leakage. During read operations, the selected word line transitions to a read voltage while unselected lines maintain the unselected voltage, optimizing both power efficiency and read performance without increasing structural complexity
2Device complexity
If cross-point memory arrays without isolation elements are used, then device complexity is reduced, but first read latency increases when transitioning from standby to read mode
Solution Approach 1:
The patent applies preliminary action by pre-biasing word lines and bit lines to an unselected voltage level before read operations. This preliminary biasing establishes a stable baseline state that minimizes leakage currents during standby mode while preparing the memory array for rapid transition to read mode, thereby reducing both power consumption and first read latency without requiring isolation elements
3Loss of energy
If unselected voltage biasing is applied during standby and read mode transition, then leakage currents are reduced and power consumption decreases, but additional control circuitry is required
Solution Approach 1:
The patent applies universality by designing the biasing circuitry to serve multiple functions: it provides standby power reduction, enables rapid transition to read mode, and simplifies the sensing path. The same unselected voltage biasing mechanism operates during both standby and read mode transitions, reducing the need for separate control circuits and minimizing additional device complexity while achieving significant power savings
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes power consumption and reduces first read latency by limiting leakage currents and simplifying the sensing path, enabling efficient operation of non-volatile storage systems without the need for isolation elements.
Implementation Method 1
In response to a suitable voltage, a conductive filament may be formed in the metal oxide such that there is one or more conductive paths from the top electrode to the bottom electrode of the variable resistance memory element. The conductive filament lowers the resistance of the variable resistance memory element.
Implementation Method 2
Application of another voltage may rupture the conductive filaments, thereby increasing the resistance of the variable resistance memory element.
Data Source
AI summary
Methods for reducing power consumption of a non-volatile storage system and reducing first read latency are described. The non-volatile storage system may include a cross-point memory array. In some embodiments, during a standby mode, the memory array may be biased such that both word lines and bit lines are set to ground. During transition of the memory array from the standby mode to a read mode, a selected word line comb may be set to a read voltage while the unselected word lines and the bit lines remain at ground. During the read mode, memory cells connected to the selected bit lines and the selected word line comb may be sensed while the selected bit lines are biased to a selected bit line voltage equal to or close to ground and the unselected bit lines are left floating after initially being set to ground.