Cross Point Memory Device Stabilizing Resistance via Bidirectional Current Limiting
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Solution Overview
Problem
Multilayer cross point memory devices face challenges in achieving stable resistance change operations across all layers due to differences in resistance change characteristics between odd and even layer memory cells, leading to inconsistent writing and reading performance.
Innovation Solution
A multilayer cross point variable resistance nonvolatile memory device is developed with a bidirectional current limiting circuit and a hierarchical bit line structure, ensuring all memory cells are oriented similarly, allowing for uniform current limiting and stable resistance value setting in low resistance writing, thereby stabilizing resistance change characteristics across all layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multilayer cross point memory device is constructed with odd and even layer memory cells, then memory capacity and integration are improved, but resistance change characteristics become inconsistent between layers
Solution Approach 1:
The patent applies local quality by introducing different bit line connection configurations for odd and even layer memory cells. Odd layer memory cells connect to bit lines through first connection nodes, while even layer memory cells connect through second connection nodes. This local differentiation compensates for the inherent structural differences between odd and even layers, ensuring consistent resistance change characteristics across all layers while maintaining high memory capacity.
2Area of stationary object
If memory cells are placed at cross points of bit lines and word lines in a multilayer structure, then integration density is improved, but leakage current to unselected memory cells increases
Solution Approach 1:
The patent segments the bit line connections by creating separate first connection nodes for odd layer memory cells and second connection nodes for even layer memory cells. This segmentation allows independent control and optimization of connection paths, reducing unwanted current paths to unselected memory cells while maintaining high integration density through the cross point structure.
3Manufacturing precision
If uniform current limiting is applied to all memory cells, then resistance value setting stability is improved, but device complexity increases due to additional circuits
Solution Approach 1:
The patent implements a universal current limiting mechanism that operates across all memory cells through the standardized connection architecture. The first and second connection nodes serve multiple functions: they provide current limiting, enable uniform resistance value setting, and maintain compatibility with the cross point structure. This multi-functionality achieves stable resistance value setting without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables stable resistance change operations in all layers, ensuring consistent low resistance writing and high resistance writing capabilities, reducing leakage current and maintaining memory cell performance across the device.
Implementation Method 1
a variable resistance element reversibly changing between at least two states including a low resistance state and a high resistance state by application of voltages of different polarities
Implementation Method 2
a bidirectional current steering element connected in series with the variable resistance element and having nonlinear current-voltage characteristics
Data Source
AI summary
A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell (51) is placed at a different one of cross points of bit lines (53) in an X direction and word lines (52) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements (57, 58) switch electrical connection and disconnection between a global bit line (56) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit (92) having parallel-connected P-type current limiting element (91) and N-type current limiting element (90) is provided between the global bit line and the switch elements.