Cross Point Memory Control via Address-Based Parameter Selection
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Solution Overview
Problem
In cross-point memory arrays, variations in effective impedance and memory cell operational parameters across different locations lead to increased memory access latency and energy consumption, as well as potential errors due to inconsistent current and voltage delivery.
Innovation Solution
An apparatus and method that select control parameter values based on the address of a target memory cell, accommodating variations in impedance and operational parameters by determining and storing these values in a lookup table, which are then used to optimize source voltages and currents, reducing latency and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform control parameters are used across the memory array, then device complexity is reduced, but memory access latency and energy consumption increase due to impedance variations
Solution Approach 1:
The patent applies local quality by dividing the memory array into multiple regions and assigning different control parameter values to each region based on its specific impedance characteristics. This allows each region to be optimized independently, reducing memory access latency without significantly increasing overall system complexity.
Solution Approach 2:
The patent implements preliminary action by pre-calculating and storing optimal control parameter values for each region in a lookup table before memory operations occur. This pre-computation approach eliminates the need for complex real-time calculations, thereby reducing access latency while maintaining manageable device complexity.
2Device complexity
If uniform control parameters are used across the memory array, then device complexity is reduced, but energy consumption increases due to inconsistent current and voltage delivery
Solution Approach 1:
The patent applies local quality by tailoring control parameters to specific regions of the memory array, ensuring that each region receives optimized voltage and current levels. This reduces energy waste from over-driving certain regions while under-driving others, thereby lowering overall energy consumption without requiring complex dynamic adjustment mechanisms.
Solution Approach 2:
The patent implements parameter changes by adjusting control parameters such as voltage levels and pulse widths based on regional impedance characteristics. These parameter optimizations ensure efficient energy utilization across different memory regions, reducing total energy consumption while maintaining uniform control architecture.
3Ease of operation
If uniform control parameters are used across the memory array, then ease of operation is maintained, but reliability decreases due to potential errors from inconsistent delivery
Solution Approach 1:
The patent applies local quality by implementing region-specific control parameters that compensate for impedance variations across the memory array. This ensures consistent voltage and current delivery to each memory cell regardless of its location, thereby improving reliability without requiring complex real-time adjustment mechanisms that would reduce ease of operation.
Solution Approach 2:
The patent implements preliminary action by pre-determining and storing optimized control parameters for each region in a lookup table. This approach maintains ease of operation by keeping the control logic simple while improving reliability through location-aware parameter selection that compensates for impedance variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces memory access latency and energy consumption by ensuring closer nominal operating values for a greater portion of the memory array, minimizing errors, and extending the operational life of memory cells.
Implementation Method 1
The cross point, e.g., phase change, memory stores information on the memory element by changing the phase of the memory element between amorphous and crystalline phases
Implementation Method 2
The chalcogenide material may exhibit either a crystalline or an amorphous phase, exhibiting a low or high conductivity
Data Source
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AI summary
The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.