Cross-Point Memory Cells With Band-Structure Engineered Diodes
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Solution Overview
Problem
Conventional memory devices, such as DRAM and SRAM, require significant semiconductor real estate, limiting bit density, while cross-point memory faces challenges with cross-talk between adjacent cells, hindering the achievement of high integration and low real estate consumption.
Innovation Solution
The development of cross-point memory cells with band-structure engineered diodes, utilizing stacked thin dielectric films to enable current passage while minimizing cross-talk, and vertically stacking memory cells to reduce real estate consumption, using low-temperature deposition processes to avoid thermal damage and incorporate materials like Ge2Se2Te5 and metal oxides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cross-point memory cells are closely packed to reduce real estate consumption, then area efficiency improves, but cross-talk between adjacent cells increases
Solution Approach 1:
The patent introduces diodes as intermediary elements positioned between adjacent memory cells. These diodes act as current guides that confine current flow to specific pathways, preventing current from spilling into neighboring cells. The diode structure with its asymmetric conduction properties serves as a mediator that enables close packing while maintaining electrical isolation between cells.
Solution Approach 2:
The patent implements local quality by creating asymmetric current conduction properties at specific locations within the memory cell structure. The diode regions are engineered with different conduction characteristics in different directions, allowing current to flow preferentially through desired paths while blocking unwanted current to adjacent cells. This local asymmetry resolves the cross-talk issue without requiring increased cell spacing.
2Ease of manufacture
If conventional memory devices are used to achieve high integration, then manufacturing maturity is maintained, but real estate consumption increases
Solution Approach 1:
The patent transitions from planar memory cell layouts to vertically stacked three-dimensional structures. By stacking multiple memory cell layers in the vertical dimension, the invention achieves higher bit density without increasing the horizontal footprint. This dimensional transition allows conventional manufacturing processes to be applied to a more space-efficient architecture, resolving the contradiction between manufacturing ease and area consumption.
3Speed
If high current is applied to program memory cells quickly, then programming speed improves, but thermal damage to materials increases
Solution Approach 1:
The patent introduces diodes as intermediary current-guiding structures that enable efficient current confinement during programming operations. By directing current precisely through the intended memory cell pathways and preventing current leakage, the diodes reduce the total current required for programming. This intermediary structure allows faster programming speeds while limiting thermal generation, as the confined current path minimizes resistive heating in surrounding materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-density, low-cost, and high-performance nonvolatile memory with reduced real estate consumption, achieving bit densities not previously possible, while minimizing thermally-induced damage and leveraging the stability of chalcogenides and metal oxides.
Implementation Method 1
stacked thin dielectric films to enable current passage
Implementation Method 2
band-structure engineered diodes, utilizing stacked thin dielectric films to enable current passage
Implementation Method 3
using low-temperature deposition processes to avoid thermal damage
Data Source
AI summary
Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.