Cross Point Memory Cell Distributed Diodes Sneak Path Leakage
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Solution Overview
Problem
Three-dimensional memory devices face challenges in reducing parasitic current leakage and sneak paths due to the limited diode area relative to the memory layer, which affects the efficiency and accuracy of memory cell operation.
Innovation Solution
The implementation of cross point memory cells with two distributed diodes, where each diode is shared among multiple memory cells, intercepts sneak paths and enhances current flow through a larger diode area relative to the memory layer, reducing parasitic leakage by grouping memory cells and using resistivity switching materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single diode is used in series with a memory layer in each cell, then the device complexity is reduced, but parasitic current leakage and sneak paths increase
Solution Approach 1:
The patent divides the diode structure into distributed diodes arranged in a cross-point configuration. Instead of using a single diode per memory cell, multiple diodes are distributed across the memory array, with each diode serving multiple memory cells. This segmentation approach reduces parasitic current leakage by creating distinct current paths while maintaining manageable device complexity through shared diode structures.
Solution Approach 2:
Each distributed diode in the cross-point configuration serves multiple memory cells simultaneously. A single diode is shared among multiple memory cells, allowing the same diode structure to perform the function of current steering for several different memory locations. This multi-functionality reduces the total number of diodes required while effectively suppressing parasitic leakage paths.
2Productivity
If the diode area is kept small relative to the memory layer, then the memory cell density is improved, but current flow control and accuracy deteriorate
Solution Approach 1:
The patent transitions from a planar diode configuration to a three-dimensional cross-point architecture. Distributed diodes are arranged in multiple layers and dimensions, allowing current to be controlled through vertical and horizontal paths. This dimensional expansion enables small diode footprints to effectively control current flow across larger memory layers, maintaining both high density and precise current control.
Solution Approach 2:
The cross-point configuration creates localized current control zones at each intersection of bit lines and word lines. Each distributed diode provides precise current steering at its specific location, ensuring that current flows only through the intended memory cell. This local quality control maintains accuracy even as diode area remains small relative to the overall memory layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for stronger current application to the memory layer, minimizes parasitic leakage, and improves the accuracy of memory cell operation by ensuring current flows only through the intended path, thereby enhancing the overall performance of three-dimensional memory arrays.
Implementation Method 1
cross point memory cells with two distributed diodes, where each diode is shared among multiple memory cells, intercepts sneak paths and enhances current flow through a larger diode area relative to the memory layer
Implementation Method 2
each memory cell of the plurality of memory cells comprises a resistivity switching material
Data Source
AI summary
A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.