Hierarchical Cross-Point Memory Array Leak Current Reduction
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Solution Overview
Problem
Non-volatile memory cells in data storage devices often generate unwanted current during operations, leading to inefficiencies and errors in reading data due to leak currents, which affect the reliability and efficiency of memory usage.
Innovation Solution
A cross-point array of non-volatile memory cells is arranged with a selection circuit that activates one block of memory cells while deactivating another, using block selection elements programmed to specific resistive states to reduce leak current by controlling current access, allowing precise reading of logical states with minimized unwanted current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory cells are used for data storage, then data retention without operational power is improved, but unwanted leak current is generated during operations
Solution Approach 1:
The memory array is divided into multiple blocks, each with its own block selection elements. This segmentation allows individual blocks to be activated or deactivated independently, enabling precise control over which memory cells can conduct current during read operations, thereby reducing unwanted leak current from non-selected blocks.
Solution Approach 2:
Block selection elements are introduced as intermediary components between the read circuit and the memory cells. These selection elements act as gates that control current flow, allowing the read circuit to access only the intended memory cells while preventing leak current from other blocks, thus resolving the contradiction between data retention and leak current reduction.
2Object-generated harmful factors
If block selection elements are programmed to control current access, then leak current is reduced, but device complexity increases
Solution Approach 1:
The block selection elements serve multiple functions: they act as address decoders to select specific memory blocks, as current gates to reduce leak current, and as part of the overall memory addressing scheme. This multi-functionality reduces the need for separate control circuits, thereby managing device complexity while achieving leak current reduction.
3Measurement precision
If only selected memory cells are accessed, then reading precision is improved, but access time increases due to block activation/deactivation
Solution Approach 1:
The block selection elements are pre-configured with the appropriate resistive states corresponding to the desired memory block addresses. This preliminary configuration allows the read circuit to immediately access the correct block without requiring time-consuming activation/deactivation sequences, thereby maintaining fast access times while achieving precise reading of selected cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces unwanted leak current, enhancing the reliability and efficiency of data reading by ensuring only selected memory cells are accessed, thereby improving memory array operations and data retrieval precision.
Implementation Method 1
programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells
Implementation Method 2
A read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current
Data Source
AI summary
A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.