Cross Point Memory Device with Distributed Schottky Diodes and MESFET Biasing
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Solution Overview
Problem
Cross point memory arrays face significant leakage currents through half-selected memory cells during write and read operations, and the use of Schottky diodes as selectors leads to read margin degradation due to voltage drops across these diodes, reducing the effective resistance ratio of memory elements.
Innovation Solution
A cross point memory device design featuring distributed Schottky diodes and MESFETs along access lines, where the Schottky diodes act as selectors and MESFETs provide a biasing current to compensate for voltage drops, enhancing the read margin by amplifying the resistance ratio of memory elements without increasing the area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a Schottky diode is used as a selector device in a 1D1R memory cell, then sneak currents are suppressed and area footprint is reduced, but read margin degrades due to voltage drop across the diode
Solution Approach 1:
An n-type semiconductor layer is introduced as an intermediary component between the Schottky diode selector and the resistive memory element. This semiconductor layer forms a MESFET structure with the metal layer, creating a controlled current path that compensates for the voltage drop across the Schottky diode during read operations, thereby restoring the read margin while maintaining sneak current suppression
Solution Approach 2:
The metal layer serves multiple functions: it acts as the anode of the Schottky diode selector device and simultaneously functions as the gate of the MESFET. This multi-functionality allows the structure to provide both sneak current suppression through the diode and read margin enhancement through the MESFET's voltage control capability
2Area of stationary object
If a Schottky diode is used as a selector device in a 1D1R memory cell, then the area footprint is reduced by removing the select transistor, but read margin degrades
Solution Approach 1:
The n-type semiconductor layer acts as an intermediary that enables read margin enhancement without requiring a separate select transistor. By forming a MESFET structure with the existing metal layer, it provides voltage-controlled current regulation that compensates for diode voltage drop while maintaining the compact 1D1R architecture
Solution Approach 2:
The semiconductor layer allows dynamic control of the current path resistance through voltage applied to the metal layer gate. This parameter change capability enables compensation for the fixed voltage drop across the Schottky diode, effectively restoring the read margin in the compact 1D1R structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses sneak currents and mitigates read margin degradation, achieving an amplified resistance ratio and improved read margin while maintaining a compact footprint, and supports selective programming of memory cells with reduced power loss.
Implementation Method 1
Each first access line includes a metal layer and a semiconductor layer extending continuously in the first direction to define a distributed Schottky diode forming a respective selector device of each memory cell
Implementation Method 2
The internal nodes of each pair of consecutive memory cells along each respective first access line are connected by a respective segment of the semiconductor layer defining a semiconductor channel configured to be gated by the metal layer of its associated first access line
Data Source
AI summary
A cross point memory device includes: first access lines and second access lines defining a plurality of cross points; and a memory cell connected between the first access lines and the second access lines at each cross point and including a resistive memory element switchable between a first resistance state and a second resistance state. Each first access line includes a metal layer and a semiconductor layer extending continuously in the first direction to define a distributed Schottky diode forming a respective selector device of each memory cell. Internal nodes of each pair of consecutive memory cells along each respective first access line are connected by a respective segment of the semiconductor layer defining a semiconductor channel configured to be gated by the metal layer of its associated first access line. The memory device also includes read circuitry configured to read the resistive memory element of a selected memory cell.