Cross-Point Memory Pillar Stacks via Selective Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming cross-point arrays in semiconductor devices result in uncontrolled variations in pillar structures, leading to limited memory cell scaling, low yield, and high manufacturing costs due to collateral etching and tapered surfaces during anisotropic etch processes.
Innovation Solution
The formation of a two-dimensional array of resistive memory elements in a cross-point configuration using a selective deposition process within via cavities, with a pillar stack structure comprising a selector material pillar and a memory material pillar, separated by barrier layers to control lateral dimensions and prevent interdiffusion, allowing for precise control of electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If anisotropic etch process is used to form cross-point arrays, then access lines can be formed, but collateral etching occurs causing uncontrolled variations in pillar structures
Solution Approach 1:
A mandrel structure is introduced as an intermediary element during the formation process. The mandrel serves as a temporary structure that defines the pillar boundaries through deposition, preventing collateral etching. After the selector and memory layers are formed, the mandrel is removed, leaving precisely defined pillar structures with controlled dimensions and uniform electrical properties.
Solution Approach 2:
The mandrel structure is formed in advance before the selector and memory material layers are deposited. This preliminary action establishes the geometric boundaries and prevents unwanted lateral growth or etching during subsequent processing steps, ensuring uniform pillar structures are formed before the actual memory materials are in place.
2Productivity
If conventional formation methods are used, then cross-point arrays can be created, but tapered surfaces are formed leading to limited memory cell scaling
Solution Approach 1:
The mandrel acts as a mediating structure that enables vertical deposition of selector and memory layers without the lateral tapering that occurs in conventional etch-based methods. The mandrel's vertical sidewalls provide a template for forming pillars with uniform cross-sectional area throughout their height, enabling precise control of memory cell dimensions and facilitating scaling to smaller geometries.
Solution Approach 2:
The patent replaces the mechanical/chemical etching process that creates tapered surfaces with a deposition-based approach using a mandrel template. Instead of removing material to define pillars, material is deposited conformally on the mandrel, creating vertically uniform pillar structures that can be precisely controlled in dimension and scaled to smaller sizes.
3Ease of manufacture
If conventional methods are used, then arrays can be formed, but uncontrolled variations lead to low yield and high manufacturing costs
Solution Approach 1:
The mandrel structure serves as a controlling intermediary that ensures uniform deposition of selector and memory materials across all pillar locations. By providing identical geometric boundaries for each pillar, the mandrel eliminates uncontrolled variations in pillar dimensions and material thickness, resulting in uniform electrical properties throughout the array and improved manufacturing yield.
Solution Approach 2:
The mandrel enables precise local control of material deposition at each pillar location. Each pillar receives exactly the right amount of selector and memory material conformally deposited on its mandrel template, ensuring local uniformity in electrical properties. This local quality control across all pillars leads to consistent device performance and reduced manufacturing variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes variations in electrical properties, enhances yield, and reduces manufacturing costs by ensuring uniform electrical characteristics and precise control over pillar dimensions, thereby facilitating scalable memory cell development.
Implementation Method 1
one of the respective lower pillar structure and upper pillar structure comprises a selector material pillar exhibiting a non-linear switching characteristic
Implementation Method 2
each pillar stack structure comprises an intermediate barrier material plate located between the respective lower pillar structure and the respective upper pillar structure and comprising a diffusion barrier material that prevents intermixing of materials
Data Source
AI summary
A via-level dielectric material layer is formed over a first dielectric material layer embedding a first conductive structure. A via cavity is formed through the via-level dielectric material layer. A least one straight sidewall vertically extends from a closed upper periphery of the via cavity at a top surface of the via-level dielectric material layer to a closed lower periphery of the via cavity that is adjoined to a top surface of the first conductive structure. A pillar stack structure is formed in the via cavity by sequentially forming a set of material portions containing a lower pillar structure and an upper pillar structure. The lower pillar structure and the upper pillar structure include a selector material pillar and a memory material pillar. A second conductive structure may be formed on a top surface of the pillar stack structure. The pillar stack structure may be used in an array configuration.