Cross-Point Memory Read Disturb Mitigation via Dynamic Capacitance Control
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Solution Overview
Problem
As memory cell arrays scale, read disturb issues arise due to increased effective capacitance in phase change memory cross-point arrays, leading to weak programming and susceptibility to noise during read operations, necessitating a method to mitigate these effects while maintaining sense margin.
Innovation Solution
The system and method involve maintaining coupling of selected word lines to a voltage source during sensing intervals, using local WL select switches to control effective capacitance and reduce write back time, and employing a partial SET pulse to address read disturb, thereby minimizing read latency and maintaining sense margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell arrays are scaled to increase density, then storage capacity is improved, but read disturb issues worsen due to increased effective capacitance
Solution Approach 1:
The patent applies dynamics by making the word line coupling state changeable - the selected word line is dynamically coupled to the voltage source during the sensing interval, then decoupled during the write-back interval. This dynamic control of capacitance coupling allows the system to adapt to different operational phases, reducing read disturb while maintaining sense margin in scaled memory arrays
Solution Approach 2:
The patent changes the electrical parameter of capacitance coupling by controlling the switch state. During sensing, the word line is coupled (higher capacitance) to maintain sense margin. During write-back, the word line is decoupled (lower effective capacitance) to reduce read disturb. This parameter change resolves the contradiction between reliability and storage density
2Reliability
If the word line is decoupled during sensing to reduce read disturb, then read disturb is reduced, but sense margin deteriorates
Solution Approach 1:
The patent uses periodic action by dividing the read operation into distinct time intervals with different coupling states. During the sensing interval, the word line is coupled to maintain sense margin. During the write-back interval, the word line is decoupled to reduce read disturb. This periodic switching resolves the contradiction by applying different coupling conditions at different times
3Reliability
If write-back operations are extended to fully address read disturb, then read disturb mitigation is improved, but read latency increases
Solution Approach 1:
The patent applies partial action by implementing a controlled write-back operation that is sufficient to mitigate read disturb but limited in duration to minimize latency impact. The write-back is applied for a specific time interval after sensing, providing just enough correction without excessive processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces read disturb and maintains sense margin by controlling effective capacitance and write back operations, enhancing the reliability of read operations in phase change memory cross-point arrays.
Implementation Method 1
the phase change memory stores information on the memory element by changing the phase of the memory element between amorphous and crystalline phases
Implementation Method 2
Snap back is a property of the composite memory element that results in an abrupt change in conductivity and an associated abrupt change in the voltage across the memory element
Implementation Method 3
The chalcogenide material may exhibit either a crystalline or an amorphous phase, exhibiting a low or high conductivity
Data Source
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AI summary
The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.