Cross-Point Memory Read Sequencing for Lower ECC Overhead
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Solution Overview
Problem
Cross-point type memory devices face challenges in achieving low bit error rates due to varying error rates between memory cells at different layers, leading to increased chip area and power consumption for error correction in existing semiconductor storage systems.
Innovation Solution
The semiconductor storage device alternates between reading from memory cells at different layers within each slice, balancing bit error rates to reduce overall error rates and optimize ECC circuit requirements, thereby minimizing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed for all memory cells uniformly, then bit error rates can be corrected, but chip area and power consumption increase due to excessive ECC circuit requirements
Solution Approach 1:
The patent applies different error correction strategies to different memory cell groups based on their specific error characteristics. Memory cells are divided into multiple groups, and each group receives error correction processing tailored to its observed bit error rate pattern, rather than applying uniform error correction to all cells. This localized approach reduces overall ECC circuit requirements while maintaining reliability.
Solution Approach 2:
The memory cell array is segmented into multiple groups for differential error correction processing. By dividing the memory cells into separate groups and applying error correction selectively to each group based on their individual error characteristics, the system reduces the total ECC circuit area compared to uniform error correction across all cells.
2Reliability
If error correction is performed for all memory cells uniformly, then bit error rates can be corrected, but power consumption increases due to excessive ECC circuit operation
Solution Approach 1:
The patent implements localized error correction by dividing memory cells into groups and applying error correction processing only where needed based on observed error patterns. This selective approach reduces the power consumption of ECC circuits compared to uniform error correction across all memory cells, while still maintaining acceptable bit error rates.
Solution Approach 2:
The system performs error correction partially rather than comprehensively for all memory cells. By applying error correction only to memory cell groups that exhibit higher error rates, the system achieves acceptable reliability with reduced power consumption from ECC circuit operation.
3Loss of information
If memory cells at different layers are read sequentially, then all data can be retrieved, but operating time increases
Solution Approach 1:
The patent implements periodic switching between reading from different layers of memory cells. Instead of sequentially reading all cells in one layer before moving to the next, the system periodically alternates between layers during the read operation. This periodic action balances the bit error rates accumulated from different layers and reduces the total operating time while ensuring complete data retrieval.
Data Source
AI summary
Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the third direction; a plurality of second region wirings provided between the second region memory cells; and a control circuit capable of executing a reading operation.