Cross-Point Memory Reference Voltage Generation
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Solution Overview
Problem
In phase change memory arrays, generating a reference voltage for read operations requires externally generated voltages, which increases die size and energy consumption due to the need for conductive paths to sense circuitry.
Innovation Solution
A system and method to locally produce a reference voltage using inherent capacitances associated with word lines and sense circuitry, with optional adjustment capacitance from unselected global word lines or trim capacitor circuitry, allowing for noise rejection and optimization of sense margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If externally generated reference voltages are used for read operations, then the memory array can perform sensing operations, but the die size increases due to the need for conductive paths to sense circuitry
Solution Approach 1:
The patent merges the reference voltage generation function with the local bit line structure by utilizing the inherent capacitance of the selected word line and sense circuitry. This integration eliminates the need for separate external reference voltage generation circuits and their associated conductive paths, thereby reducing die size while maintaining sensing capability.
Solution Approach 2:
The patent enables the local bit line and sense circuitry to generate their own reference voltage using the inherent capacitance of the selected word line. This self-service approach eliminates dependence on external voltage sources and reduces the need for additional conductive paths, thereby reducing die size without compromising sensing precision.
2Measurement precision
If externally generated reference voltages are used for read operations, then the memory array can perform sensing operations, but energy consumption increases due to conductive paths to sense circuitry
Solution Approach 1:
The patent combines the reference voltage generation function with the local bit line structure, eliminating the need for separate external voltage sources and their associated conductive paths. This merger reduces energy consumption by removing the energy required to maintain and drive these external paths while preserving sensing capability.
Solution Approach 2:
The local bit line and sense circuitry generate their own reference voltage using inherent capacitance, making the system self-sufficient. This eliminates energy consumption associated with external voltage generation and transmission paths, reducing overall energy usage while maintaining sensing precision.
3Area of stationary object
If inherent capacitances of word lines are used to generate reference voltage locally, then die size and energy consumption are reduced, but noise immunity must be maintained
Solution Approach 1:
The patent employs feedback mechanisms where the sense circuitry monitors the voltage on the local bit line and adjusts the reference voltage generation process accordingly. This feedback ensures that noise is detected and compensated for, maintaining noise immunity while using local capacitance-based reference voltage generation that reduces die size.
Solution Approach 2:
The patent introduces intermediary elements such as decoupling capacitors and noise filtering circuitry between the inherent capacitance sources and the sense amplifier. These intermediaries filter out noise while allowing the reference voltage to be generated locally, thus maintaining noise immunity without sacrificing the space savings of local generation.
4Loss of energy
If inherent capacitances are used for reference voltage generation, then external voltage paths are eliminated, but sense margins between set and reset voltages must be optimized
Solution Approach 1:
The patent implements dynamic adjustment mechanisms that allow the reference voltage to be tuned in real-time based on the actual state of the memory cells being read. This dynamic optimization ensures that sense margins are maximized for both set and reset states, maintaining measurement precision while using energy-efficient local reference voltage generation.
Solution Approach 2:
The patent utilizes parameter changes in the capacitance values and voltage levels to optimize the reference voltage generation process. By adjusting these parameters, the system can maintain optimal sense margins between set and reset voltages while benefiting from the reduced energy consumption of local reference voltage generation without external paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces die size and energy consumption by generating a reference voltage locally, enhancing noise immunity and optimizing sense margins between set and reset voltages in phase change memory arrays.
Implementation Method 1
generating a reference voltage for read operations requires externally generated voltages, which increases die size and energy consumption due to the need for conductive paths to sense circuitry
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.