Cross-Point Memory Device Sneak Current Suppression
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Solution Overview
Problem
Cross-point nonvolatile semiconductor memory devices face reduced detection sensitivity due to sneak current issues during resistance value reading, particularly in large-scale arrays, where the offset component current is significant, affecting reading accuracy and scalability.
Innovation Solution
The implementation of a cross-point nonvolatile semiconductor memory device with a dual cross-point cell array structure, including dummy bit lines and offset detection cells, which allows for the suppression of sneak current by applying a current through unselected word lines via dummy bit lines, thereby enhancing signal-to-noise ratio during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a cross-point cell array is scaled up to increase storage capacity, then large-scale integration is achieved, but sneak current increases and detection sensitivity deteriorates
Solution Approach 1:
The cell array is segmented into multiple blocks, with each block containing a subset of word lines and bit lines that can be independently controlled. This segmentation limits the number of active memory cells during read operations, thereby reducing sneak current while maintaining overall large storage capacity across multiple blocks
Solution Approach 2:
Sense amplifiers are introduced as intermediary components between the memory cells and the read circuitry. These sense amplifiers amplify the small current signals from selected memory cells while rejecting sneak current, thereby improving detection sensitivity in large-scale arrays
2Measurement precision
If voltage is applied to read resistance value of a memory cell, then detection is enabled, but sneak current flows through parallel memory cells causing offset current
Solution Approach 1:
Before performing a read operation on a selected memory cell, the word lines and bit lines are pre-charged to specific voltage levels, and unselected word lines are pre-discharged. This preliminary action establishes a known baseline state that helps cancel out sneak current effects during the actual read operation
Solution Approach 2:
The read circuit employs feedback mechanisms where the detected current is compared against reference levels, and the difference signal is used to determine the resistance state. This feedback approach allows the circuit to distinguish between sneak current (which appears in both differential measurements) and the actual signal from the selected cell
3Measurement precision
If dummy bit lines and offset detection cells are added to suppress sneak current, then reading accuracy improves, but device complexity increases
Solution Approach 1:
Dummy bit lines are designed to serve multiple functions: they provide sneak current cancellation paths, act as reference lines for sense amplifier operation, and can be used for cell selection in certain modes. This multi-functionality reduces the need for separate dedicated structures for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves reading accuracy and scalability by reducing sneak current components, allowing for high-precision resistance state determination and increased signal-to-noise ratio, even in large-scale arrays.
Implementation Method 1
a variable resistance element which changes a resistance value in response to application of a voltage signal between two terminals
Implementation Method 2
determines a resistance state of the selected cell based on a current which flows through the selected bit line
Data Source
AI summary
A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.