Cross-Point Memory Tile Segmentation for Power and Access Optimization

The memory device is divided into multiple tiles, where each tile contains memory cells from multiple layers. This segmentation allows the memory system to access only the specific tile containing the target memory cell, rather than activating all layers across the entire memory array. By segmenting the memory space into tiles, the patent reduces the number of simultaneously active memory cells during access operations, thereby lowering power consumption while maintaining the ability to access any memory cell across multiple layers.

The patent implements local quality by enabling different regions (tiles) of the memory device to be independently accessed. When a memory cell in a specific tile needs to be accessed, only that tile is activated with its associated word lines and bit lines, while other tiles remain inactive. This localized access approach ensures that power consumption is concentrated only in the necessary region rather than being distributed across the entire memory array, thus reducing overall power consumption while preserving full access capacity.

By segmenting the memory device into tiles where each tile contains memory cells from multiple layers, the patent enables parallel access within a tile. When accessing memory cells, the system can simultaneously activate multiple layers within the same tile using different bit line sets, rather than sequentially accessing each layer. This segmentation-based parallel access mechanism increases access capacity while reducing the time required to complete multi-layer access operations.

The patent introduces a tile dimension as an additional organizational level beyond traditional layer-based addressing. This dimensional change allows the memory system to address memory cells through a hierarchical structure where tiles group multiple layers together. By adding this organizational dimension, the system can perform broader parallel access operations across layers within a tile while maintaining fine-grained control, thus improving access time without sacrificing access capacity.

The patent divides the high-density cross-point array into multiple tiles, where each tile contains a manageable subset of memory cells from multiple layers. This segmentation simplifies the addressing complexity by limiting the scope of address decoding to within each tile rather than across the entire large array. The tile-based organization allows the memory controller to manage high-density storage while maintaining relatively simple addressing logic for each individual tile, thus achieving high memory density without proportionally increasing addressing complexity.

The patent adds a tile dimension to the traditional layer-based memory organization, creating a hierarchical addressing structure. Instead of directly addressing memory cells across all layers in a flat structure, the system first addresses tiles and then accesses specific layers within selected tiles. This dimensional addition organizes the high-density cross-point array into manageable units, reducing the complexity of address generation and decoding while preserving the high memory density achieved through multi-layer stacking.