Cross-point Memory Voltage Clamp Circuit for Fast Read Start-up
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Solution Overview
Problem
Conventional voltage systems and power source devices for nonvolatile memory devices are not suitable for low current consumption and high-speed stable operation due to their inability to achieve high-speed rising of output voltage during start-up.
Innovation Solution
A cross-point variable resistance nonvolatile memory device with a cross-point memory cell array, including variable resistance elements and current steering elements, a reference voltage generation circuit, a differential amplifier circuit, and a feedback controlled bit line voltage clamp circuit, which enables rapid setting and stabilization of the best voltage for reading memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional voltage systems and power source devices are used, then the memory device can operate, but the output voltage rising speed during start-up is slow
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a predetermined voltage level before the actual read operation begins. The bit line voltage clamp circuit prepares the voltage in advance, so when the read operation starts, the voltage is already at the optimal level, eliminating the slow rising period and achieving high-speed start-up while maintaining stable operation.
2Use of energy by moving object
If the bit line voltage is not quickly set to optimal level, then the circuit can start, but power consumption increases due to prolonged operation phase
Solution Approach 1:
The patent employs periodic action through the bit line voltage clamp circuit that operates in controlled phases: during the read operation, the clamp circuit actively maintains the bit line voltage at the optimal level, and during non-read phases, it releases control. This periodic activation ensures voltage is quickly set when needed and reduces unnecessary power consumption when the operation is not active, achieving both low power consumption and fast voltage setting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high-speed and stable operation while reducing power consumption by quickly setting the optimal voltage for memory cell reading, enhancing low power consumption and high-speed performance.
Implementation Method 1
a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state when different voltages are applied to the variable resistance element
Implementation Method 2
a current steering element that is connected in series to the variable resistance element and has nonlinear current-voltage characteristics
Implementation Method 3
a feedback controlled bit line voltage clamp circuit which applies a first current to a selected bit line until a voltage of a selected bit line reaches a voltage determined with reference to an output voltage of the differential amplifier circuit
Data Source
AI summary
A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell.