Cross-Point Memory Array Voltage Regulation for Data Integrity
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Solution Overview
Problem
Conventional memory architectures face challenges in scaling down memory array and cell dimensions, leading to increased resistance in word lines and bit lines, which results in voltage drops and potential damage, and are not well-suited for operating memory cells without gate-like structures, limiting their effectiveness in smaller geometries.
Innovation Solution
A two-terminal cross-point memory array with discrete re-writeable non-volatile memory elements using mixed valence conductive oxides and electrolytic tunnel barriers, where access signal generators adjust voltage magnitudes based on line characteristics to compensate for voltage drops and isolate un-selected memory elements, maintaining data integrity during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory array dimensions are scaled down, then memory density is improved, but resistance of word lines and bit lines increases causing voltage drops
Solution Approach 1:
The patent applies parameter changes by adjusting the access voltage magnitude based on the position of memory elements along the array line. The access signal generator modifies voltage parameters to compensate for position-dependent resistance variations, ensuring stable operation despite scaling-induced resistance increases.
Solution Approach 2:
The patent implements feedback through the access signal generator that monitors or calculates position-dependent voltage drops and adjusts the access voltage accordingly. This feedback mechanism ensures that each memory element receives the appropriate voltage level to maintain reliable operation across the scaled array.
2Quantity of substance
If memory array dimensions are scaled down, then memory density is improved, but increased resistance may damage array lines
Solution Approach 1:
The patent changes the voltage parameter dynamically based on memory element position to maintain safe current density levels. By adjusting access voltage magnitude, the system prevents excessive current flow that could damage scaled-down array lines while still enabling effective memory operations.
Solution Approach 2:
The access signal generator performs preliminary anti-action by pre-adjusting the access voltage to compensate for position-dependent resistance before current flows through the memory element. This prevents harmful current density spikes that could damage the array lines during scaling.
3Reliability
If conventional memory architectures with gate structures are used, then data retention in un-selected cells is improved, but they are not suitable for gateless memory cells
Solution Approach 1:
The patent achieves universality by creating an access mechanism that works with gateless memory cells while still providing data retention functionality. The position-dependent voltage adjustment approach serves multiple functions: enabling access to gateless cells and preventing inadvertent operations in un-selected cells, replacing the need for gate structures.
Solution Approach 2:
The patent extracts the gate structure from the memory cell design, creating gateless memory cells. The gate-like protection function is separated from the memory cell itself and implemented at the array level through position-dependent voltage control, allowing simpler cell structures while maintaining system functionality.
4Reliability
If position-dependent voltage compensation is applied, then data operation reliability is improved, but access signal generator complexity increases
Solution Approach 1:
The access signal generator implements parameter changes by adjusting voltage magnitude based on memory element position. While this adds some complexity, the approach maintains reliability by ensuring each position receives appropriate voltage levels, and the complexity is justified by the improved data operation reliability across the scaled array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reliable data access and retention across scaled dimensions by compensating for voltage drops and preventing inadvertent data operations in un-selected memory elements, ensuring the integrity of stored data during scaling down of memory technologies.
Implementation Method 1
an electrolytic tunnel barrier and one or more layers of a conductive metal oxide material that includes mobile oxygen ions... application of a write voltage across the memory element causes ion transport between the electrolytic tunnel barrier and the conductive metal oxide material
Implementation Method 2
The memory element can assume different resistive states, including but not limited to a high resistive state and a low resistive state... the resistive value of the memory element is not disturbed by the application of the access signal
Data Source
AI summary
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.