Cross-Point Anti-Fuse OTP Memory with MIS Capacitors
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Solution Overview
Problem
Existing cross-point anti-fuse one-time programmable (OTP) memories face challenges such as significant process complexity, array leakage current, and reliability issues, while also requiring additional process steps and masks, which are not compatible with standard CMOS flows, and suffer from program disturb and gate dielectric breakdown.
Innovation Solution
A cross-point anti-fuse OTP memory design that uses Metal-Insulator-Semiconductor (MIS) capacitors with no source/drain implants connected to the channel, following a standard CMOS process flow, with optional floating p+ regions and thicker gate dielectrics to reduce leakage and improve reliability, and employs a bitline implant mask to form active stripes without additional critical masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-point anti-fuse OTP memory is implemented with source/drain implants connected to the channel, then programming capability is achieved, but program disturb and gate dielectric breakdown occur
Solution Approach 1:
The patent extracts and removes the source/drain implant regions from the memory cell structure. By eliminating these implants entirely, the patent prevents program disturb and gate dielectric breakdown while maintaining the anti-fuse programming mechanism through direct gate dielectric breakdown without requiring connected source/drain regions.
Solution Approach 2:
Instead of using source/drain implants to enable programming (conventional approach), the patent inverts the approach by using direct gate dielectric breakdown without source/drain connections. This inversion eliminates the harmful effects of source/drain regions while achieving the desired programming functionality.
2Reliability
If additional process steps and masks are added to achieve cross-point anti-fuse memory, then memory functionality is achieved, but process complexity increases
Solution Approach 1:
The patent uses standard CMOS process steps that serve multiple functions. The same process steps used for creating standard CMOS devices are also used for creating the anti-fuse memory cells, eliminating the need for additional specialized process steps and masks.
Solution Approach 2:
The standard CMOS process flow automatically creates the necessary structures for anti-fuse memory without requiring additional process steps. The existing process capabilities are leveraged to self-create the memory functionality.
3Ease of operation
If source and drain regions extend under sidewall spacers to connect to channel region, then transistor operation is enabled, but array leakage current increases
Solution Approach 1:
The patent extracts and removes the source/drain regions entirely from the memory cell structure. By eliminating these regions, the patent eliminates the leakage current path that would exist through extended source/drain regions under sidewall spacers, while maintaining memory functionality through the anti-fuse mechanism.
4Reliability
If thicker gate dielectric is used to prevent breakdown, then reliability improves, but cell area increases
Solution Approach 1:
The patent applies different dielectric thicknesses to different regions of the gate. The gate dielectric is thinner in regions where breakdown is desired for programming and thicker in regions where leakage prevention is needed, optimizing both reliability and area efficiency through localized dielectric properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a compact memory array with low leakage current and improved program reliability, maintaining logic CMOS compatibility without extra process steps or masks, and reduces cell size and program disturb issues.
Implementation Method 1
The gate dielectric before programming and the P+/N+ diode formed after programming can have questionable quality
Implementation Method 2
Due to impact ionization and other high voltage mechanisms, the floating source/drain can be charged up to a voltage well above ground
Data Source
AI summary
A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.