Cross-Point OTP Memory Array Using MIS Capacitors
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Solution Overview
Problem
Existing cross-point one-time programmable (OTP) anti-fuse memories for silicon-on-insulator processes face challenges such as significant process complexity, array leakage current, and reliability issues, particularly due to the need for additional critical implant masks and questionable gate dielectric quality, which are not compatible with standard CMOS flows.
Innovation Solution
The development of a cross-point memory array using metal-insulator-semiconductor (MIS) capacitors with a standard CMOS process flow, where bitlines are formed using a dedicated implant mask, and the absence of source/drain implants connected to the channel, along with a thicker gate dielectric to reduce leakage and program disturb, and the use of polysilicon gate pre-doping to eliminate p+ regions, enhancing cell density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cross-point OTP memory is implemented with standard CMOS process, then manufacturing compatibility is improved, but process complexity increases due to additional critical implant masks
Solution Approach 1:
The patent extracts the bitline formation step from the standard CMOS process flow by using a dedicated implant mask, separating this critical step to reduce overall process complexity while maintaining CMOS compatibility
Solution Approach 2:
The patent applies preliminary doping to the polysilicon gate before forming the memory structure, which eliminates the need for additional p+ region formation steps later in the process, thereby reducing process complexity
2Reliability
If source/drain implants are connected to channel in cross-point memory, then device functionality is achieved, but program disturb and leakage current increase
Solution Approach 1:
The patent removes the source/drain implant connection to the channel in cross-point memory structures, eliminating the mechanism that causes program disturb and leakage current while maintaining essential device functionality through alternative conduction paths
Solution Approach 2:
The patent converts the potential harm of floating source/drain regions by deliberately leaving them undoped, which prevents impact ionization and high voltage charging effects that would otherwise cause program disturb in unselected cells
3Quantity of substance
If thinner gate dielectric is used in cross-point memory, then device density is improved, but leakage current and reliability issues increase
Solution Approach 1:
The patent optimizes the gate dielectric thickness parameter to a specific range that balances density and leakage, using thicker dielectric where needed to prevent leakage while maintaining overall cell density through efficient layout
4Manufacturing precision
If additional critical implant masks are used in cross-point memory, then precise doping is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the bitline doping step using a dedicated implant mask, performing this critical doping operation separately to achieve precise doping profiles without requiring multiple overlapping masks in the standard CMOS flow
Solution Approach 2:
The patent performs preliminary doping of polysilicon gates before memory structure formation, establishing precise doping profiles early in the process to eliminate the need for additional critical implant masks later
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more compact, reliable, and leakage-resistant memory array that complies with standard CMOS design rules without additional process steps, improving cell size and reducing leakage currents during programming and read operations.
Implementation Method 1
the gate dielectric before programming and the P+/N+ diode formed after programming
Implementation Method 2
a thicker gate dielectric to reduce leakage and program disturb
Data Source
AI summary
A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology.