Cross-Point ReRAM Forming via Segmented Voltage Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In cross-point memory arrays without isolation elements, forming non-volatile storage elements is challenging due to significant current draw from lower resistance states, making it difficult to form additional elements, and leakage currents vary with biasing voltage and temperature, affecting switching behavior and array efficiency.
Innovation Solution
A three-dimensional cross-point memory array with vertical bit lines, where non-volatile storage elements are formed in a specific order, with current limiting and resetting, and biased voltages are applied to minimize waste currents, allowing for controlled forming and reduced voltage requirements, eliminating the need for diodes and simplifying manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile storage elements are formed in parallel without isolation elements, then the number of addressable memory elements increases, but significant current draw from lower resistance states makes it difficult to form additional elements
Solution Approach 1:
The patent segments the forming process into sequential stages where memory elements are formed in groups rather than all at once. Isolation elements are selectively formed between groups of memory elements to prevent current leakage between groups during forming operations, enabling parallel formation of multiple elements while controlling current draw through temporal and spatial segmentation.
Solution Approach 2:
The patent applies preliminary isolation by forming isolation elements between memory element groups before performing parallel forming operations. This preliminary action prevents harmful current leakage paths from establishing themselves during the forming process, allowing safe parallel formation of multiple storage elements without excessive current draw.
2Ease of manufacture
If forming operations are performed without current limiting, then the forming process is simpler, but leakage currents vary with biasing voltage and temperature affecting switching behavior
Solution Approach 1:
The patent implements current limiting by controlling the voltage parameters applied during forming operations. By adjusting voltage levels and applying them selectively to different groups of memory elements, the system maintains consistent current flow that compensates for leakage current variations due to temperature and biasing conditions, ensuring reliable switching behavior while maintaining a relatively simple forming process.
3Object-generated harmful factors
If diodes are used to reduce parasitic currents, then leakage currents are minimized, but device complexity increases and manufacturing is simplified
Solution Approach 1:
The patent extracts and removes the need for diodes by using alternative current control mechanisms. Instead of relying on diodic structures to block parasitic currents, the system uses selective voltage application and isolation element formation to achieve the same current control effect, thereby reducing device complexity and manufacturing steps while still minimizing leakage currents.
4Reliability
If higher voltages are applied during forming, then conductive filaments form more reliably, but voltage requirements increase and manufacturing becomes more complex
Solution Approach 1:
The patent uses periodic voltage application in a controlled sequence during the forming process. By applying voltages in alternating phases to different memory element groups and using isolation elements to control current paths, the system achieves reliable conductive filament formation at lower voltage levels without requiring complex voltage control mechanisms, as the periodic action naturally manages current distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time and voltage needed for forming non-volatile storage elements, minimizes leakage currents, and increases the number of addressable memory elements without errors, enhancing the array's efficiency and reducing manufacturing complexity.
Implementation Method 1
One theory that is used to explain the FORMING mechanism, as well as the switching mechanism to RESET and SET the variable resistance memory elements, is that one or more conductive filaments are formed by the application of a voltage to the variable resistance memory elements. In response to a suitable voltage, a conductive filament may be formed in the metal oxide such that there is one or more conductive paths from the top electrode to the bottom electrode of the variable resistance memory element.
Implementation Method 2
variable resistance memory elements that may be set to either a low resistance state or a high resistance state. The state of such a memory element is typically changed by proper voltages being placed on the intersecting conductors.
Data Source
AI summary
Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.