Cross-Point Resistive Memory Leakage Mitigation
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Solution Overview
Problem
Resistance-change memory cells in cross-point arrays face interference from leakage current, which impedes the implementation of high-density memory cell arrays and causes read errors, especially when switches, diodes, or other select devices are not used to control excessive leakage.
Innovation Solution
A cross-point memory array devoid of switches, diodes, or other select devices is implemented, with resistance-change memory cells having an area of 4F2, where F denotes the minimum working dimension, and a controller that matches the size of data objects to memory tiles, appending error correcting and detecting code bytes to ensure all memory cells are selected during operations, thereby mitigating leakage current interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switches, diodes, or other select devices are used to control leakage current, then read errors are prevented, but memory density and cell area are reduced
Solution Approach 1:
The patent removes switches, diodes, and other select devices from the cross-point array structure. By extracting these control components, the memory cell area is reduced to 4F², enabling higher memory density while using alternative methods (sensing amplifiers and voltage thresholds) to prevent read errors.
Solution Approach 2:
The patent introduces sensing amplifiers as intermediary components that detect and amplify the small current signals from selected memory cells. These amplifiers act as mediators between the cross-point array and the read circuitry, enabling reliable data retrieval without requiring select devices at each cross-point.
2Quantity of substance
If cross-point arrays are designed with high density (4F² cell area), then memory capacity increases, but leakage current interference worsens
Solution Approach 1:
The patent applies different properties to different parts of the system: the memory cells themselves are minimized to 4F² for high density, while sensing amplifiers with specific voltage thresholds are applied at the readout nodes to locally compensate for leakage current effects. This localized quality enhancement allows high-density cells to operate reliably despite leakage.
Solution Approach 2:
The patent changes the operating parameters of the cross-point array by using voltage threshold detection and sensing amplifier biasing to distinguish valid data signals from leakage current. By adjusting these electrical parameters, the system can tolerate higher leakage levels that would otherwise cause read errors in high-density configurations.
3Area of moving object
If select devices are removed to increase memory density, then cell area decreases, but leakage current control becomes more difficult
Solution Approach 1:
The patent merges the functions of select devices and sensing circuitry into a unified sensing amplifier system. Instead of having separate select transistors and sense amplifiers, the sensing amplifiers directly interface with the cross-point array nodes, combining selection and sensing functions to simplify the overall device structure while maintaining leakage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased memory density without the need for additional control components, effectively reducing leakage current and preventing read errors by ensuring all memory cells are utilized during data access operations.
Implementation Method 1
resistance-change memory cells having an area of 4F2
Data Source
AI summary
A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.