Cross-Point Memory Wear-Leveling via Data Relocation
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Solution Overview
Problem
Current cross-point (X3D) memory technology does not implement a wear-leveling mechanism, leading to uneven wear of memory cells, which compromises the performance and lifespan of the memory system as some cells wear out faster than others, making the system unusable when a critical number of worn-out cells are present.
Innovation Solution
Configuring X3D memory into small memory units (SMUs) for hot data and large memory units (LMUs) for warm or cold data, and performing wear-leveling by switching the storage locations of hot data with warm/cold data to ensure even wear across memory cells, while maintaining the relative sequential order of data structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If wear-leveling operations are performed to evenly distribute wear across memory cells, then the lifespan of the memory system is extended, but the complexity of the memory management system increases
Solution Approach 1:
The memory system is segmented into multiple memory pools (first pool, second pool, third pool) that can be independently managed. Each pool contains memory units that can be selectively activated or deactivated based on wear levels, allowing the system to distribute write operations across multiple segments to extend overall lifespan while maintaining manageable complexity through modular organization.
Solution Approach 2:
The memory management system dynamically adjusts the activation state of memory pools based on wear levels. The controller monitors wear metrics and dynamically transitions pools between active and inactive states, enabling adaptive wear distribution without requiring complex permanent reconfiguration of the entire memory system.
2Productivity
If memory units are frequently rewritten to maintain data availability, then system performance is maintained, but the wear on individual memory cells increases rapidly
Solution Approach 1:
The system discards heavily worn memory units by deactivating entire memory pools when wear thresholds are exceeded. Inactive pools are later recovered and reused when less worn pools become available through wear-leveling operations, allowing the system to maintain performance by continuously rotating between pools while extending the usable life of individual memory cells.
Solution Approach 2:
The system performs preliminary wear-leveling operations by deactivating worn pools before they fail completely. This proactive approach allows the controller to redistribute data and wear across fresh pools before critical failure occurs, maintaining system performance while preventing catastrophic memory cell degradation.
3Reliability
If worn memory cells are deactivated to maintain reliability, then system reliability improves, but the available storage capacity decreases
Solution Approach 1:
Memory pools serve multiple functions: they act as active storage when fresh, transition to inactive state when worn, and are later recovered for reuse. This multi-functional design allows the same physical memory units to contribute to both reliability (by being deactivated when worn) and capacity (by being recovered and reused), eliminating the need to permanently sacrifice worn cells.
Solution Approach 2:
Instead of permanently discarding worn memory pools, the system temporarily deactivates them and recovers them through wear-leveling operations. This approach maintains reliability by keeping worn pools inactive during critical periods while preserving their storage capacity for future reuse when less worn pools are available.
Data Source
AI summary
A method performed by a processor to improve wear-leveling in a cross-point (X3D) memory, comprises detecting, by a processor coupled to the X3D memory, a trigger event, wherein the X3D memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.